I hope to start messing with my new CPLD setup over the holidays.

I've tinkered around with FPGA in the past...even though it was a gigantic pain to get everything setup. I'm hoping my CPLD experience won't be as bad.

So, I have the ATF1504AS and the official Altera USB cable. I also have a PLCC-44 to DIP 44 converter.

1) What language are you guys using to program these CPLD's? I've seen WinCUPL mentioned (I'm assuming CUPL is the language).

2) This CPLD will be used for glue logic but I'd like to learn a "hello world" with it by flashing some LED's. Are there any tutorials out there for something like that? I have actually searched online but *EVERYTHING* I find is centered around VHDL/Verilog and FPGA. Perhaps my search skills are failing me.

3) 64 macrocells doesn't sound like it can do much. But I admit, I'm still not 100% sure what a macrocell actually is. How many macrocells do you guys think would be needed for a BASIC VGA controller? Nothing fancy...just driving some pixels from SRAM. I'm planning for a future project where I will either use a larger CPLD or a small FPGA.

Thanks!

_________________
Cat; the other white meat.

There is some useful information in the ATF15xxx family overview, including a picture of their macrocell.

Each output pin requires a macrocell to drive it. In addition, each internal bit of state (i.e. a flip/flop) requires another macrocell. Another limitation is the 5 product terms per macrocell. If you need more, then neighbouring macrocells will be used to provide more product terms.

To see if a particular device is suitable, I recommend downloading the design tools first, design your project, and run the synthesis to see what device it will fit. Usually the tools will inform you about number of macrocells used for what purpose, allowing you to try to improve the design to make it fit better. Personally, I always use verilog for CPLD design, but that's a personal preference.

Thanks for the information. I actually have been reading the datasheet for that part. But, it's written (IMHO) for people who already have a good understanding of CPLD's and PLD's in general.

I've programmed (a little) with VHDL and thought it was OK. The Verilog I've seen looks more "C-like" which is nice considering I'm a C/C++/Java developer. So, I have no issues with learning Verilog.

It also sounds like my assumptions are true...there just isn't much you can do with 64 macrocells. But, that's OK because I didn't buy the ATF1504AS for VGA work. I'm sure it can handle some complex glue logic (I intend to map some of the Apple IIe memory maps for 128K).

_________________
Cat; the other white meat.

I agree, the Atmel datasheet isn't very good at explaining the details. I've been more impressed with Xilinx CPLD datasheets. Even though those are not the devices you intend to use, the general principles are very similar, so they may still be helpful in understanding.

Also, if you have the design tools, you could start with some very simple stuff, like blinking LEDs and doing simple logic functions, and then look at how things were implemented.

That's actually what I'm wanting to do.

What tools do you suggest?

_________________
Cat; the other white meat.

You'll need tools from Atmel, since these are the only ones that know how to synthesize for their devices. From their site, it looks like you have a choice between WinCUPL, and ProChip Designer. Only the ProChip Designer can do VHDL/Verilog, and it requires a license. Not sure if you can get a free license or if it's all paid.

Ugh...this is what I hated about the FPGA software. Took an Act of Congress to get a license to install the 30 GIGS of software. :-/

But thanks for the suggestions!

_________________
Cat; the other white meat.

The tools from Xilinx also require a few gigs of software, but at least their license is free for all small devices.

WinCUPL's language is ABEL. Although its not as main stream as VHDL/verilog, It is not hard to learn. I programmed my DEC-1 and wait-state generator (22V10 GAL), SBC-3, and SBC-4's CPLD's using ABEL. The SBC-3's CPLD has 108 macrocells and generated a 320x200 display with 8 bits per pixel using the PHI2 lo half-cycle and did the system memory buffering/decoding.

All of my ABEL code is on my website if you want some examples.

http://sbc.rictor.org/decoder.html

http://sbc.rictor.org/wsgen.html

http://sbc.rictor.org/download/sbc3.zip

Cheers!

Daryl

_________________
Please visit my website -> https://sbc.rictor.org/

Awesome! Thanks!

Oh, do you remember how many of those 108 macrocells was used for the SBC3?

_________________
Cat; the other white meat.

107 or 108. I kept adding features until I ran out of room.

Daryl

_________________
Please visit my website -> https://sbc.rictor.org/

WinCUPL is the lingua franca of Atmel CPLDs, and may also be used to program GALs. You can download WinCUPL from here. I attached a copy of the CUPL reference manual.


My suggestion would be to start by writing some simple combinatorial logic in WinCUPL so you can learn how to use the language and the tools. It's like anything else: you develop skill and insight by making mistakes and fixing them. Once you get the hang of it you can design something that will give you some blinkenlights.


You'd be amazed how much you can fit into 64 macrocells. One of the things I learned was to let the fitter, which is the part of the software that actually synthesizes your design into a particular device, to assign the pins. If you assign pin numbers yourself you could develop a design that simulates but won't fit. The fitter generates a report (<something>.fit) that will tell you what got assigned to what. You can then take that information and permanently assign pins in your source file so as to retain them in the event you make some minor changes. That's how I did POC V2's logic.

Note that the ATF1504AS has 32 uncommitted I/O pins. It is possible to use the JTAG pins as I/Os, but doing so will make it impossible to reprogram the device with the Atmel or Altera programmer. Also note that the 1504 has an assigned clock input (GCLK1, on pin 43) and assigned reset input (GCLR, on pin 1). These two should be permanently assigned in your CUPL source file, with statements such as the following:

Code:

pin     1 = RESB;                                 /* system reset          */
pin    43 = PHI2;                                 /* system clock          */

For other inputs and outputs, omit the actual pin number from the assignment, which will cause the fitter to work out the assignments for you. The fitter's goal is to minimize the use of logic resources, as well as actually fit the design to the particular device in use. It is certainly possible for one to do the work of the fitter by studying the internal structure of the part and then making the proper assignments. It's a very tedious process, however.

In addition to the PIN assignment statement, there is also the PINNODE statement, which doesn't use a pin number. PINNODE is how you set up buried logic, e.g., flip-flops. For example:

Code:

pinnode   = [blatch0..3];                         /* bank address latches                 */

The above, which is from the source code for POC V2's logic, sets up four latches named blatch to capture the 65C816's A16-A19 address components:

Code:

/*
========================
A16-A19 GENERATION LOGIC
========================
*/
[blatch0..3].LE = bavalid;                        /* open latches         */
[blatch0..3].L  = bavalid & [D0..3];              /* capture bank         */
bank0     = [blatch0..3]:'b'0000;                 /* 1 if bank is $00     */
extram    = !bank0;                               /* 1 if bank is not $00 */

In the above, bavalid is a pin node that goes true when the '816 is emitting a valid bank address on D0-D7, that is, when the expression (VDA # VPA) & !PHI2 is true, where # is logical OR and & is logical AND. The suffix .LE opens a D-type latch and the suffix .L refers to the latch content proper. All of this is explained in the CUPL reference manual.

At the beginning of your source file, you can insert some statements that affect how WinCUPL processes your logic and fits your design to the device:

Code:

property   atmel {cascade_logic=on};
property   atmel {logic_doubling=off};
property   atmel {output_fast=off};
property   atmel {pin_keep=on};
property   atmel {preassign=keep};
property   atmel {security=off};
property   atmel {xor_synthesis=on};

All of this is explained in the help files. Start with the above settings and then play around with them to see how they affect the process. Note that the output_fast property affects the slew rate of the CPLD's outputs. Play with it and observe and output with the 'scope to see what happens.

Your general workflow in WinCUPL is to create a project, write your CUPL code (CUPL means "compiled universal programming language") with the built-in editor, compile, fix any compilation errors, and then simulate your design. Within the simulator, you can set inputs, run the simulation and see how the outputs are affected. Once you are satisfied with your design you can run the Atmel ISP program to program your CPLD.

If you do a search here you should be able to find other posts about this stuff.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

@BDD

Thanks for that information! I have a lot of reading to do.

That's a good point about the JTAG and clk/reset pins. So, since I want to be able to program in-circuit, I actually need to subtract 6 pins for JTAG and 2 for clk/reset. Does that mean I only have 24 I/O pins? If so, that's going to suck.

_________________
Cat; the other white meat.

I bought the Olimex iCE40 FPGA development board (Olimex have a tutorial on driving VGA using Verilog with that board) before I realised that it only had 24 pins unassigned, which is enough for A15-0, D7-0 and nothing else, not even RWB, so I bought the HX8K development board directly from Lattice, which has ~120 I/Os available. I've been loving the IceStorm tools, which solve the large download problem if you want to use iCE40 FPGAs.

I think it is 4 pins for the JTAG.
My quick pin count for the 1504 is
4 for Vcc
4 grounds
4 JTAG
4 input only
and up to 28 I/O