hi

I'm trying to interface device that runs at 1mhz frequency with 6502 running a bit faster - i need only write acces and i'm forced to user 6502, not 65c02
i came up with simple interface - two latches - one on data lines, adn one on adress lines going to mentioned device, but no luck - i have chip select and R/W lines wired together (when acces then write) and nothing happens, device doesn't respond...
mentioned device is 6581 SID, and host platform is atari 65xe if anyone wonders...

best regards,

Candle (Sebastian Bartkowicz)

> i have chip select and R/W lines wired together (when acces then write)
> and nothing happens, device doesn't respond...

I think that's where your problem is. The R/W\ and address have to be valid at least 45ns before CS\ goes true. So in your case, the R/W\ line was high (meaning "read") 45ns before your CS\ went down, so you got some bus conflict and no write.

I thought I had a full data sheet here for the 6581, but I can't seem to find it. I got this little bit of timing info from a timing diagram for the 6581 in a C64 manual.

Garth

ok, so what you saying is that i should rewire r/w line to ground and that wuould be all...
but.. assuming i had bus conflict (which happens before first write to sid) then after first possibly unsuccessful write to sid, next one should be valid (writes repeats whenever sid 02 is going down, latches on data and address lines are permanently enabled)
maybe i should disable sid after first write? or it is ok to repeat write on every bus cycle?

candle

Without taking time to familiarize myself with the SID, I expect things won't work right if you write to it over and over like that. I don't see any problem with just grounding the R/W\ line if you don't even have to read a status register, but enabling the part all the time may mean re-starting certain functions over and over, not letting timers run their course and things like that.

Bill Mensch said that at MOS, they did the first year and a half of product testing in the 70's on a home-made fixture, without parametric testing. If they were going to mark a part for 1MHz, it had to run a 2MHz, etc.. Later the fixture was replaced with a Century tester. After that, Commodore forced MOS, their own supplier, into a very difficult financial situation, and subsequently bought them out for pennies on the dollar in a very unethical scheme dreamed up by Jack Tramiel. Anyway, you might find that the 1MHz part will run at 1.7 MHz without any special interface buffering as your glue logic isn't too slow or have too many logic levels.

One other thing-- is there a continuous square wave coming in on the SID's phase-2 pin? Some parts won't work right without it. The 6551 is one example. Phase 2 is needed for some internal operations, not just coordinating bus transactions.

Garth

i've rewired r/w signal to ground, and CS signal is gated throught pulse extender (LS123) so it should now work just fine.. nevertheless i would rather check firs - there is no such thing as prottotype board around here, and i have to etch final board every time i made mistake - it's going to ruin me soon
i need that buffering, even if this actual device can run at 2 or even 3MHz i don't care - this must be done at 1MHz to maintain compatibility with existing software (existing on c64 standard atarian procedure - to cut out and adept to atari

anyway thanks alot for all information, i'll post ready protel project (or pdf version of it) if anybody wants to look at this, but this is designed as replacement board for atari POKEY chip... well anyway

best regards

candle

When writing to the SID chip, deactivate the RDY signal for one clock cycle; this will add one wait-state to the bus cycle, which will give the SID chip the time it needs to respond to the bus state. This is, in fact, the very purpose of the RDY signal.

--
Samuel A. Falvo II

generic 6502, not CMOS version can be stopped by RDY only when READ is done, and i have to use 6502..

I wasn't aware of that. One other alternative, I think, is to latch the relavent address bits during Ph1, then latch the data bus during the rising edge of ph2. If the SID chip is being addressed, bring _CS low at the rising edge of ph2, and then release it two cycles later. Then the only software requirement is that it cannot write twice to the SID chip consecutively. That is:



might possibly violate the SID-interface timing, as the latches may or may not have settled long enough for the SID chip to respond. However:



is guaranteed to work OK -- the _CS pin for the SID chip is negated as the operand for the second LDA is being fetched.

This should work for all but the most pathologically extreme cases of writing to the SID chip. This method also has the advantage of not halting the processor on wait-states.

> One other alternative, I think, is to latch the relavent address bits
> during Ph1, then latch the data bus during the rising edge of ph2.

If I understand you right, you may need to modify this. The address and R/W\ lines as set up by the 6502 are guaranteed to be valid well before the rising edge of phase 2; but according to the Synertek data book, the write data is not guaranteed to be valid until 100ns after the rising edge of phase 2 for the 2MHz 6502. I doubt the MOS data book would be much different. A simple delay circuit might do the job nicely though. You can use a simple RC followed by a schmitt trigger to delay the rising edge of the input to the data-latching circuit. You might want about 22pF following a 10K trimmer pot. The input of the gate will provide some additional capacitance, and the gate, especially with the schmitt trigger, will add perhaps another 15ns beyond the RC delay.

You are correct; I meant to say latched during ph2 high, but I was thinking edge-triggering for some reason. Probably because I was subconsciously thinking of how to implement the delay circuit for the _CS line.

--
Samuel A. Falvo II

before you go any futher i want to explain some thinngs....

this whole "device" is done as replacement board for pokey chip in atari
it includes two pokeys and two sids, everything is placed at $D200 page
sid must be run at 1mhz not because it wouldn't stand up 1.79 from atari, but because that is its speed on c64 - music files are taken from c64 as they are, only sid address changes...
at http://alan.umcs.lublin.pl/~candle/schematic.pdf are schematics of version i'll be etching soon - if you have any objection please let me know

regards

candle

Have you completed the board yet ?

- something I thought of
- depending on how reliably it has to work, this is may be a clock domain crossing problem (1.79 to 1.0 or 1.023 ?) The 1.023M might be sync'd to the 1.79 so no problem, but if a separate oscillator cirut is in use you might have to worry about metastability.

-how about simply latching all the signals, but then rather than feeding CS\ right to the SID, feed in into a FF pulse generator clocked by the 1MHz so it generates a single pulse to the SID on an CS edge. If there's a falling edge on both the CS\ and 1MHz then spit out a pulse to use as CS\ for the SID.

Rob