DerTrueForce wrote:
This way, the vector being pulled is $80 on both bytes. That line is not shorted to Vcc, because it goes low at other times.
I'm not sure which line you're referring to as "not shorted to Vcc," but the
single-stepping has given you an excellent clue. You'll do well to get to the bottom of this.
Data line D7 shorted to Vcc could result in $80 on both bytes -- but so too could address line A0 shorted to Vcc. (In such a case the ROM would fetch the high-byte even in the cycle during which it's "trying" to fetch the low-byte. IOW the high-byte would get fetched twice -- $8080.)
I suggest you concentrate on the cycle during which the low byte of the Reset vector is being fetched. All being well, the CPU sends an out address, and this stimulus reaches the ROM in the form of address lines and control lines such as chip-select. Verify these signals at the receiving end, not just at the CPU where they begin the journey.
If the ROM receives the correct stimulus, and assuming its contents are correct, then next you need to verify the ROM output. Once again you should verify that the signals reach their destination (the CPU).
Bear in mind that LED's don't verify that the logic highs and lows are as high and low as they should be. If you're unable to find anything conspicuously amiss re the cycle during which the low byte of the Reset vector is being fetched, then check all the signals again but using a multimeter. Be on the lookout for voltages hovering around 30-70% of Vcc -- they're a sign of trouble. Healthy signals should be close to zero or close to 5V. (The indicator LED's you put on the data bus will reduce the logic high voltage somewhat. Make sure the load isn't excessive.)
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