Thanks for that!
I was wondering, how are you handling the 128K? Can, for example, Microsoft BASIC peek/poke to the expanded RAM?
Thanks.
The 65C02 address bus, data bus and R/!W pin are connected straight to the SRAM chip. It's possible to jumper the !CE line of the SRAM chip to pin P265 or P27 of the Propeller. In the schematics the optional line from the Prop to !CE is called !RAMEN (RAM Enable Not). The Propeller can pull this pin low during Phi2 to let the 65C02 use the SRAM chip as ROM or RAM. The Apple1SRAM project demonstrates this.
To use the upper half of the SRAM chip, the Propeller has to control the 17th address line A16 as well as !CE. A16 can be jumpered to P25 or P26. There are no projects that use A16 at this time. How the Propeller uses A16, is up to the software.
For example, though it's not possible to emulate a C64 without extra hardware, having the 128K SRAM chip will help with a possible future C64 replica design: The Propeller would intercept write operations to what would normally be the I/O port in the 6510, and switch A16 on or off based on the current address and based on the last value written to the output port, to emulate the bank switching between RAM and ROM (Kernal, Basic interpreter and character generator ROM).
The SRAM chip is really only necessary because the Propeller only has 32K of hub memory. The reason that it's a 128KB chip and not a 64KB chip, is that 64K SRAM chips are surprisingly hard to find.
As for BASIC: It would be impossible to do a PEEK or POKE into the upper half of a 128K memory chip, because basically a PEEK or POKE translates to a LDA or STA instruction in absolute mode, and of course you can only use a 16 bit address with those instructions, not a 17 bit address, so that's quite impossible. Yes, it might be possible to expand a BASIC interpreter to control the bank switching logic and accept a 17 bit address for PEEK and POKE, but that would be a lot of extra trouble that's not needed; after all, the bank switching logic is probably based on writing a magic value to an I/O port, and BASIC can do that too: you would just have to do 2 pokes instead of one. But again: it's all up to the Propeller firmware and I have no application in mind for the upper half of the SRAM at this time.
Final words: I could have used a 256K chip and used all three free pins of the Propeller to control it, but I figured that would be feature creep. The bank switching may not be very useful anyway because there's no address translation hardware: depending on A16 you can either see the first 64K or the second 64K in the chip. If you'd want to create a system that runs Fuzix, you would probably need some hardware that lets you see all the upper memory through a small window in the memory map. That would require extra hardware so it's something that will just not be possible with the motherboard. A small amount of hardware could be put on an expansion card (or a breadboard) to allow multiple megabytes of bank-switched RAM (or ROM) but there are so many other ideas that have a higher priority in my head.
===Jac
