Hi, new member here.

As far as I know, the overflow bit doesn't affect any instruction in the 6502 and 6510 CPUs. Hence, there seems to be no point in clearing the V bit explicitly.
Is there a useful purpose for CLV anyhow? After all, there are no instructions for setting V, setting Z or clearing Z either.
Am I overlooking anything?

_________________
I trust my somewhat flawed English is comprehensible to all.

Actually, your English is excellent.

The 6502 has an input pin labeled SOB, pin 38. Here is an excerpt from the WDC 65C02 datasheet:


Its safe to assume that the CLV instruction is used to reset this status register bit after the SOB input is detected.

Hope that clears this up!

Daryl

The overflow flag tells if the sign bit of a signed arithmetic result is wrong. You'll see the earlier discussion on this if you down, under "General Discussions", down to "Carry and Overflow flags..." The URL is: http://www.6502.org/forum/viewtopic.php?t=62 . C and Z are touched on there too, but not with the same emphasis as V. When you're ready for more confusion, there's another one where we discussed the (in)validity of V in decimal arithmetic!

Welcome to the forum.

So that's what I forgot all about. Thanks for reminding me. The R6502 datasheet doesn't advise against using it, but I can see why 65C02 does.
Still CLV serves no purpose for the 6510.

@Garth:
Thanks for your welcome.
I'm familiar with the purpose of the overflow flag, but I was strictly referring to it not being an input parameter for any instruction.

_________________
I trust my somewhat flawed English is comprehensible to all.

Remember too that, after detecting an overflow, you can take actions to correct the overflow, and use CLV to "reset" the condition so that you can resume your calculation and detect another overflow event. This won't likely be used except in multi-precision, fixed-point, signed integer math though.

Would there be any reason to clear it though, since each test of the flag (by conditional branching) will reflect the result of the last ADC or SBC (or BIT, PLP or RTI, TSB, or TRB)? None of these instructions care what it was going in, or leave the initial V value intact.

> Is there a useful purpose for CLV anyhow?

Apart from using it conjunction with SO\ (which again, has hardly ever been done and is not recommended), the only thing I can think of so far is unconditional branching on the NMOS 6502 which lacked the CMOS 65c02's BRA instruction. Before I started using the CMOS one in 1986, I occasionally did CLV BVC to substitute.

> After all, there are no instructions for setting V, setting Z or clearing Z either.

Not directly, but you can, if you must, do something like
for example

The 65C816 also includes the SEP and REP instructions. SEP can be used to set the V flag directly now, so as with C, it too can be used to indicate function return status (e.g., as the Commodore Kernal did to indicate errors).

Although, you could also set the V flag manually too this way (which is only 1 cycle longer than SEP):