Hey there. I've recently begun working on my own design for a 6502 computer. The system is based around 24 MCM4116 DRAM chips, totaling 48 KB of RAM. In order to precisely determine how to wire the 4116 chips in series, I did a test with an Arduino Uno that was successful in writing and reading from 3 chips simultaneously, as well as preforming refresh.

Now here's the problem: glue logic.

The wiring of the 4116's is similar to the 4164's in the C64. All chips have the same address bus, R/CAS and W signals, but the data I/O is different for each once. Only, unlike the C64, 8 chips only gives me 16K. That means if I want to use all 24, I need 3 pages of 16 K of memory. Then the 16K left needs room for two 6522's and at least 15KB EEPROM. I did write up a memory map:


...but I'm having difficulty figuring out exactly how to do address decoding.

I have a collection of 74 series TI logic chips, and two 74LS688 chips. I've been trying to come up with a circuit diagram similar to those I have seen for other SBC projects, but I feel like I have far more subdivisions of memory space than most people need. Enabling and disabling the 4116 chips is also going to be tricky.

If anyone has any tips for address decoder design, I'd appreciate it.

Is the DRAM just for the sport and history of it? If so, that's valid; but otherwise, there are much easier ways to do things, and SRAM is far easier to use (with no multiplexing or refresh) and inexpensively available in ICs up to 512KB each (2MB if 3.3V), far more than the 64KB memory map of a 6502. (You'll probably want to use a 32KB, ie, 32Kx8, like a 62256. See the 6502 primer, and especially now the section on address decoding.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

DRAM is mostly for the sport, and also because had a supply of it off-hand.

I saw the 32 K RAM/16 K ROM circuit earlier on your site, and it looked like the closest to what I need. That circuit gets everything divided into 3 sections, but I need some more comparisons to occur. Would this circuit work for 4 16k banks? It uses 5 NAND gates and two inverters. It may be completely wrong.

It has several problems. But first, how fast are your DRAMs, and how fast do you hope to run the computer? (I ask because it affects what types and how many levels of cascaded logic you can have. The thinner the timing margins, the harder it will be to meet them with fine-grained address decoding like having only 32 bytes for I/O.)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Welcome, pw132 -- nice to have you with us! It's clear you're off to a good start, and are getting a grasp of some of the basics. Your circuit still needs some work, though. For example, the NAND at the bottom (which drives the ROM) won't activate the ROM except when A15 and A14 are both low. But the only time A15 and A14 are both low is when the region 0 - $3FFF is addressed, and that's not what you wanted. One other detail I noticed is that you have the Φ2 signal connected as part of the circuit for bank #1 and #2, but not for #3 or the ROM. Is Φ2 needed at all in this part? Part of the reason I'm puzzled is because you haven't shown what the NAND's conect to. The DRAM's you're using have /RAS and /CAS inputs, both of which must be driven -- and with a defined timing sequence -- or else the DRAM won't respond.

There's also the issue of multiplexing. Have you planned what arrangement you'll use for that? (The C64 probably uses a pair of 74_257's, but I haven't checked.) And what do you propose in regard to a refresh scheme?

As Garth already mentioned, SRAM is far easier to use. Also, his web site provides lots of info and advice regarding SRAM. It's okay if you want to use DRAM's, but they are more complicated and also it will be somewhat harder to get info and advice.

cheers,
Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks you two for the help! I think I managed to sort-out the problems with the decoder circuit (shown below). I have two 74LS00 Quad NAND's that the circuit below uses fully. As for refresh, I'll place a manual refresh routine on a timer interrupt set for every 2 ms, which shouldn't take up huge amounts of CPU time at my planned 2MHz. This is basically the same system I used in my Ardiuno test. I've started building a test of the decoder circuit already, but it's not hooked up to the processor so I can just use it to drive testing LEDs. As for what these outputs actually connect to... that's something I'm still trying to figure out. My best idea is to use those outputs to enable pass-through for the write signal and CAS signals for a specific 16K section, using discrete transistors.

Ok, you still have:

• A bank #2 that will never go true (low) when Φ2 is high. Outside of that, A15 is getting inverted twice, so along with A14, bank #2 ends up at $C000-FFFF where you need ROM.
• The only address line going into bank #1's select is A14; so it will be selected for both $4000-7FFF and $C000-FFFF
• Bank #3's first NAND gate requires both A14 and A15 to be low, so you get 0-3FFF
• The ROM's 16K takes a low A14 and a high A15, so it's at $8000-BFFF. $FFFA-FFFF need to be in ROM though, for the vectors.

A 74HC139 might be a good way (or 74HCT, 74AC, 74ACT, but I would discourage the use of 74LS, as discussed in the 6502 primer).

How do you plan to get the I/O in?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Yeah, I tried multiple designs of decoder with the 00's after I posted that message and I didn't get any working properly. I'll look for the 74HC139, it looks exactly like what I need for splitting memory into 4 segments.

If you mean the VIA by "I/O", I'm embarrassed to say I'm not sure about that either. The first step in my mind was to get the 4-way split working. I checked the primer a bit for info on that but I'm not sure. I know the VIA has 16 registers, but the bussing required is confusing.

The circuit below shows what a '139 contains, and the Function Table shows how it behaves. Note that the Select input and all the outputs are active low. IOW when low they are said to be asserted, or true. When high they are deasserted AKA false.

The Select input is pretty simple. Select must be true (L) or else none of the outputs can be true (L).

A1 and A0 are what control the 4-way split. It's important to notice that every NAND inputs either A1 or its complement, and every NAND inputs either A0 or its complement. Things are connected such that each NAND responds to one and only one of the four possible combinations of A1 and A0.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

May be this should control DRAM...? Multiplexers (not pictured) should be switched by /RAS. R/W signal from MPU is connected direct to /W of all DRAMs. Address decoder included

EDIT: It seems, falling edge of /CAS comes too early, I will correct.

Nice. I haven't checked actual DRAM timing spec's, but the circuit looks like it should work.

It might be slightly smaller and easier to build if three-input NANDs (such as 74_10) were used to drive the CAS\ lines.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

May be so is better?

The two-stage frequency division is needed to obtain a 62.5 nS delay between the rising edge of Ф2 and falling one of /CAS to wait until MPU put data on the data bus during the writing cycle. I did not want to deal with RC Charging Circuits to achieve the delay.
Everybody may check the circuit diagram for mistakes, I will try to fix.

Update: Sorry it's been two days, but I haven't been able to work on the project til now. I got a decoder working using a '08 Quad AND and a single Quad NAND, instead of two of the 00 Quad NANDs. (I know it works cause I hooked the logical output to 4 LED's and fiddled with two input wires til it worked. ) This should provide the 16K * 4 split I need, if these signals enable/disable CAS and WE.

It looks like I need now is multiplexing(?) the A0-A15 signals into the Column/Row input the DRAM wants, as well as generating CAS/RAS, which is the biggest hurdle right now for me. Information on exactly how to do this has been difficult to find. I'll read your recent responses in more detail soon, but I had to write this in a rush.

A0÷A13 only. Address decoder copes with A14 and A15. Don't worry about /WE. There is no need to enable/disable this signal (assuming MPU only drives this line).
The multiplexing is a simple thing. All you need is multiplexers. As switching signal you can try to use /RAS or Ф2 ( in correct polarity).

Cheers, Vladimir