Without getting into programmable logic (GAL/CPLD/etc.), I'm faced with a choice of using an extra IC or having repeatable I/O addresses.

Currently, my design is using a 2:4 and 3:8 mux to get my I/O. I'm debating exactly where but for the sake of argument, let's say it will be like so:



The lowest 4 bits (A3:A0) are my 16 registers but the four bits A10:A7 would mean my I/O repeats 16 times. Correct?

I don't think that is the end of the world. But, it kinda bothers me a little. Not sure why.

Pros of leaving it this way:

1) Only two chips of glue logic. 74AC139 that feeds into the '138.
2) Only two chips means much less propagation delay.

Cons of leaving it this way:

1) *Only* 8 I/O devices. Which is a lot, really. But, I do plan on having a couple VIA's and a couple video/audio components. So I might actually eat up 8 pretty quick.

2) Repeatable I/O addresses. (This may not be a con, really).


An alternative is to leave out the 3:8 which would give me 10 I/O devices. But, tons of repeatable I/O. Meaning you could easily read/write from all 10 at once!

What are your thoughts?

BTW, this is my first SBC but I plan on keeping the speed around 1-2 MHz tops. And, expansion is important to me because I want to play around with making expansion cards like sound cards, etc.

Thanks!

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Cat; the other white meat.

I don't think there's any real downside to incomplete decoding leaving to mirrors of devices in several places - the trick is to ensure you always access devices at the specific intended addresses, so if you later update your decode and add more devices, you won't break your existing software.

It's all in the address-decoding page of the 6502 primer. Using only a 74xx00 quad NAND gate, you can have up to ten I/O ICs, 16K of RAM, and 32K of ROM. Using one additional gate (an inverter), you can swap the quantities of RAM and ROM. Keeping the decoding so simple reduces gate delays and allows for a faster maximum clock rate. Having devices show up at more than one address is not a problem. In fact, there's the rare possibility someone may want to set up two or more ICs the same way at the same time, for example to start timers in them at the same time, so it's beneficial to be able to write to both of them in the same cycle. This method allows that, although normally you'll be writing to addresses that go to only one device at a time.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Don't forget that the 138 has 3 chip selects. By wiring upper address lines to those selects you can increase the number of I/O devices without using more than 2 chips on any particular path.

Ie. for 2 x 138's and 16 I/O slots
on one 138 wire the active low output from the 139 and A13 to the active low select on the 138, the active high one pulled high
on the other the A13 goes to the active high select, the 139 to one of the low ones, and the other low select tie to 0v.

Perhaps you could use the active-high enable input on the '138 to expand one of the existing ten I/O slots?

slot 00 - $8010..801F
slot 01 - $8020..802F (2 copies)
slot 02 - $8040..804F (4 copies)
slot 03 - $8080..808F (8 copies)
slot 04 - $8100..801F (16 copies)
slot 05 - $8200..821F (32 copies)
slot 06 - $8400..841F (64 copies)
slot 07 - $8800..881F (128 copies)
slot 08 - $9000..901F (256 copies)
slot 09 - $A000..A01F (512 copies)

You'd have to use one of the slots that is 128 bytes or larger to accommodate eight 16 byte blocks from the '138 (slot 03 or above). For example, if you tie the A7 address line to the active-high enable input on the '138 you'll expand slot 03 with the following chip select outputs (for a total of 17 chip select outputs).

$8080..808F
$8090..809F
$80A0..80AF
$80B0..80BF
$80C0..80CF
$80D0..80DF
$80E0..80EF
$80F0..80FF