I seem to have run into a snag.

[neff]

What started two weeks ago as a CPU test board has quickly grown into this:

6502.org wrote:

Image no longer available: http://rdp.maclisp.org/65C02board-5s.jpg

All has seemingly gone well, to the point of figuring out how to write to the data bus.
Seeing as RWB goes high when the processor expects to read off the data bus, I figured I could take advantage of this to feed 5v to the dipswitch block, to only write when the CPU is reading off the bus. The blue slide switch toggles between connecting RWB to the high-biased side of the dipswitch block, and disconnecting it. In the picture, it is shown in the disconnect position.

All the electrical connections test okay on the meter.. but no matter what, i'm unable to set the state of D0 and D3 via the dipswitch. In addition, when the slide switch is set to connect RWB, to supply the common +5v side of the switch block, RWB never goes low while this connection is made. I've also attempted to connect the +5v side of the switch block directly to the main +5v rail, and this also yielded the same results as sourcing +5v from RWB. Only if the slide switch is set to disconnect, does RWB cycle high and low.

Any suggestions on how I can inject a byte onto the data bus only on cycles it would be reading? My approach seems to have failed thus far.

[GARTHWILSON]

Can you give a diagram of that portion.

[DerTrueForce]

I'm no expert, and the schematic would help, but:

The not being able to set D0 and D3 sounds to me like a dodgy DIP switch. Did you check that that was working?

Is R/W being connected to +5v at the DIP switch? That would cause problems like you describe. It might also damage the CPU.
What I would do looks something like this:

Code: Select all

-------------+                   +------------+                       +5v
65C02    R/W |-----------|>o--+--|/OE1        |                        |
             |                +--|/OE2        |          +---------+   |
          D0 |-------------------|O0        I0|--+-------|  DIP    |---+
          D1 |-------------------|O1        I1|--)--+----|  Switch |---+
             |                   |            |  |  |    +---------+
             |                   |            |  |  +-[3.3K]-+
             |                   |            |  |           |
             |                   |  74xx244   |  +----[3.3K]-+    
             |                   |            |              |
             |                   |            |             GND

This thing: -|>o- is a not gate.

I've only shown two data lines to make it clearer, but you'd do the same for all the data lines.

I hope you'll be able to get your board working.
I'm going to go a different way with mine(stacking boards), but that's the beauty of this hobby: near-endless variety.

EDIT: You may also have to take Phase 2(the system clock) into account. I think the 'C02s accesses are valid when Phase 2 is high. Someone else will be able to confirm that. You'd run Phase 2 and R/W into a NAND gate instead of just R/W into a NOT.

[BigDumbDinosaur]

DerTrueForce wrote:

EDIT: You may also have to take Phase 2(the system clock) into account. I think the 'C02s accesses are valid when Phase 2 is high. Someone else will be able to confirm that. You'd run Phase 2 and R/W into a NAND gate instead of just R/W into a NOT.

That is true of all members of the 6502 family.

[PaulF]

With the 6502 and 65C02 you don't nead to take Phase 2 into account, as the processor is not doing anything with the data bus when Phase 2 is low. Driving the data bus when Phase 2 is low and R/W is high is not a problem. The processor requires valid data to be present on the data bus when Phase 2 goes from high to low, and for a setup time before this. However, in a read cycle, this data can be present from the start of the cycle (When Phase 2 went low and R/W went high at the end of the previous cycle) with no ill effects.

With a 65C816, you do need to take Phase 2 into account because this processor uses the data bus to output the upper 8 bits of the address when Phase 2 is low. With a 65C816, other devices should only drive the data bus when Phase 2 is high or you will have two devices driving the bus simultaneously - this condition is called bus contention.

[neff]

Sorry about the late reply. I verified that the DIP switch indeed works, though I'm not using any sort of gate between RWB and the switch block. Here's the best I could do as far as a schematic of the area in question:

6502.org wrote:

Image no longer available: http://rdp.maclisp.org/RWBdata.png

[PaulF]

neff wrote:

In addition, when the slide switch is set to connect RWB, to supply the common +5v side of the switch block, RWB never goes low while this connection is made. I've also attempted to connect the +5v side of the switch block directly to the main +5v rail, and this also yielded the same results as sourcing +5v from RWB. Only if the slide switch is set to disconnect, does RWB cycle high and low.

Be aware that the R/W line only goes low when the processor is executing a write instruction. If the data you are feeding to the data bus does not cause the processor to execute a write instruction, the R/W line will never go low. This may be what you are experiencing.

[neff]

PaulF wrote:

Be aware that the R/W line only goes low when the processor is executing a write instruction. If the data you are feeding to the data bus does not cause the processor to execute a write instruction, the R/W line will never go low. This may be what you are experiencing.

I did a little more poking around after reading this, and you are correct. RW stays high if D0 is high, but cycles on and off when I pull D0 low. If I pull D3 high, and all others low, RW cycles at a different rate. (When single-stepping, it usually stays high for two cycles at a time, as opposed to three.) So the switch block works, and all the analog stuff checks out on the meter... turns out those two LEDs are bad.

I'll change those out, and get to work on building a NAND gate. Thanks, guys.