GARTHWILSON wrote:
I see what happened. I took the 74xx32's to be AND gates, because that's how you drew them. The '32 is an OR gate, not an AND. Here's an OR gate:
(picture)
The input side is curved, the the output comes to a little point, both unlike the AND gate.
Oh I see. For some reason Eagle CAD seems to draw it the way I posted. I will try to change it to make less confusion here.
Anyway, the circuit doesn't work and I am leaning towards that being a timing problem. The actual tested circuit has a 50ns delay between BEL and BER:
Code:
BEL 111100000000001111 (left BE=MBE)
BER 000001111111100000 (right BE)
Without the small delay in switching from one bus to the other, I got bus contention (which I originally thought was the problem). I have tested different writing pulse delays but no luck yet. Basically it should write on the rising edge of WE, but it is not doing so very often.
The first design (which worked better, but still error-prone) used a combined OE signal and put that through a NAND with the CLK on the other input to generate WE. That was stable if I only ran one processor at a time (e.g. no same-cycle access).
At time being I am testing my first CPLD designs (Lattice breakboard) to get a more dynamic logic (read: easy to change). I want to run the two processors at different speeds, so a CPLD helps in that it has its own clock. Once I get some more results I will post it here.