candle wrote:
generic 6502, not CMOS version can be stopped by RDY only when READ is done, and i have to use 6502..
I wasn't aware of that. One other alternative, I think, is to latch the relavent address bits during Ph1, then latch the data bus during the rising edge of ph2. If the SID chip is being addressed, bring _CS low at the rising edge of ph2, and then release it two cycles later. Then the only software requirement is that it cannot write twice to the SID chip consecutively. That is:
Code:
SID = $xxxx
LDA #$aa
STA SID+0
STA SID+1
might possibly violate the SID-interface timing, as the latches may or may not have settled long enough for the SID chip to respond. However:
Code:
SID = $xxxx
LDA #$aa
STA SID+0
LDA #$bb
STA SID+1
is guaranteed to work OK -- the _CS pin for the SID chip is negated as the operand for the second LDA is being fetched.
This should work for all but the most pathologically extreme cases of writing to the SID chip. This method also has the advantage of not halting the processor on wait-states.