While trying out the visual 6502 with some different ranges on branch instructions, I noticed that:

1. The decision of page crossing seems to be derived from the overflow rather than the carry
That made sense as the calculation involved 2's complement. (o/w it would consider it a page cross every time you branched backwards)
However that raises the question of how did it subtract the 'PCH'. Did it use the 'PCHDB' & 'DBADD' to increment or decrement the PCH?
--- edit Not sure if overflow is the case either. but carry alone doesn't fit

2. The offset was applied to 'alua' input of the ALU, while the 'alub' got its input from ADL (while PCL is setting it)
I found that strange as I couldn't find any connection from 'db' to 'alua'. I believed 'alua' was either '0' or 'sb'.

Welcome!

I think it's the carry. The thing to note is that for a forward branch, it's carry set which indicates page crossing, but for a backward branch it's the opposite. See line 5 of this tabulation:
http://www.visual6502.org/JSSim/expert. ... loglevel=5
Line 6 is the start of the next cycle, which would be a SYNC cycle if there was no page crossing, so line 5 has to contain the information needed to decide on that.

You're right, the 'a' input to the ALU is either zero or the special bus. But note that there are a set of pass transistors which can make SB an extension of the IDB (internal data bus) which is what's used to bring the branch offset to the ALU.
http://www.weihenstephan.org/~michaste/ ... 2/6502.jpg

Thanks for the clarification BigEd. So it must've used the MSB of the offset to determine whether the carry set or clear meant a page crossing occurred.
Funny thing I found with branching is that 'ab', I assume to be the address bus, changed in T1 (cycle 7) while the fetch clearly had the instruction already.

Right, it looks at the sign of the branch offset. It's quite a complex bit of logic, but if you look at the signal short-circuit-branch-add you can trace it back. (The first part of the branch calculation is in effect the addition of a signed byte and an unsigned byte, so neither C nor V gives you the indication that you need to calculate the high byte too.)

Not sure if the 6502 does exactly this, but a useful way to think about it is that a page crossing is marked by the carry being different than the MSB of the branch-offset. IOW, if the branch-offset is positive (i.e. MSB=0), then a HIGH carry indicates an page crossing, whereas if the branch-offset is negative (i.e. MSB=1), then a LOW carry indicates a page crossing. To then adjust the high byte, you can add the carry + a sign-extension of the branch-offset (i.e. $FF for MSB = 1 and $00 MSB=0) which effectively either adds or subtracts 1 as appropriate. Like this:


In the Visual6502 listing BigEd provided:

Line 5: alua $70 (BranchOffset) + alub $f5 (PCL) = $65 -> PCL, (alucout=1 XOR alua.bit7=0) = 1, so page crossed!
Line 6: alua $12 (PCH) + alub $00 (SignExtend(BranchOffset)) + carry (1) = $13 -> PCH
Line 7: pc = $1365

_________________
C74-6502 Website: https://c74project.com

I think I was wrong about short-circuit-branch-add - it's somewhere near the action but I'm not sure if it's central. It's certainly used as one of the many inputs to the signal which controls incrementing the PC. (This page explores some of the circuitry in the area.) We're looking for an XOR function which takes in the alu carry out (or something derived from it) and the branch offset sign bit (or something derived from it.)

I think the NMOS 6502 doesn't have the circuitry for doing a sign extend of the branch offset,
so the ALU has to increment/decrement PCH according to the MSB of the branch offset
when there is a page crossing.

Would suggest to search for a mechanism that configurates the ALU for increment/decrement
during a branch... or that loads PCH during a branch.

NMOS 6502 only has conditional branches, so it might be interesting where the output
of the multiplexer that detects the flags according to the uppermost three Bits of the Opcode
goes to.

It's just a thought...