6522 timing

[malcnorth]

I have just got a small 6522 board running at 4Mhz and I now want to up the clock rate to 14MHz (well I am planning to use a 14.318MHz Oscillator).
I have added a wait state for EPROM and I am using 15nS static RAM. When I read the W65C22S data sheet there is a timing parameter called tACR which is specified as 10nS, That is the addresse and chip select lines have to be stable 10nS before the rising edge of PHI2. The problem is addresses are not available from the CPU until 30nS after teh falling edge of phi2. Therefore at 14mHz its not possible to meet this requirement even without any decoding.

Does anybody have any insight into this? Better still a possible solution?

I have seen a design somewhere where multiple 74xx04s have been used to delay the clock is this the reason for the delay?

[GARTHWILSON]

Another problem with WDC's data sheets. Fortunately the parts have always been found to do a lot better than specified (except in the case of a bug in the '51, and one in the '22 in a shift-register mode most users don't use).

[malcnorth]

Thanks Garth. That's the reply I was hoping for.

I'm guessing the 6522 problem you are referring to is the shift register with external clock on CB1. I know about that ( I used to work for Commodore in the 70s and we had a dealer try to build a network using the 6522).

Are you suggesting that if I get the 10nS is pessimistic and that I just need to make sure the chip selects and addresses occur before phi2 rising edge?

I have some unused 74AC86s in the design which I can use to delay the clock.

Malcolm

[BigDumbDinosaur]

malcnorth wrote:

When I read the W65C22S data sheet there is a timing parameter called tACR which is specified as 10nS, That is the addresse and chip select lines have to be stable 10nS before the rising edge of PHI2. The problem is addresses are not available from the CPU until 30nS after teh falling edge of phi2.

WDC's data sheets are notorious for ambiguities like this, as well as outright errors. The fact is, as Garth noted, the stuff works at the rated frequency. You should be good to go without doing anything hinky with timing.

[GARTHWILSON]

I think the 30ns tADS is probably the pessimistic one. I think things are always ready quite a lot sooner than that. 30ns would mean that the processor can't work at all over about 16MHz; but they apparently top out at about 25MHz at room temperature, if the supporting parts are up to it.

To connect computers with the VIA's shift-register port, see my topic, "SS22: 6522 synchronous-serial interface between computers."

[malcnorth]

Interestingly that's more or less what I have got

I have added a fourth 'ATN' line. and got drivers in between.

[GARTHWILSON]

malcnorth wrote:

Interestingly that's more or less what I have got

I'm glad you got it going.

Quote:

I have added a fourth 'ATN' line. and got drivers in between.

You probably don't need the drivers, at least with the WDC 65C22S. When I tested it for output strength some years ago, each output looked approximately like a 43Ω resistor before going into current-limiting at about 50mA. That's per pin. It could pull up to 4.2 into a 220Ω load to ground, which makes for almost 85% of Vcc at 19mA! Pulling down into a 220Ω load to Vcc, it did .8V (again doing 19mA). They are much, much stronger than the specifications let on. (Again, the part is way better than the data sheet says.) Rockwell's were not symmetrical like WDC's. Each output pin of a Rockwell R65C22 could do 100mA when trying to pull down into a dead short to Vcc, but only 20mA when trying to pull up into a dead short to ground.