I have an idea that I think is doable but I'm not sure.
I'm wondering if it's possible to access the 4164/4464 DRAM in a C64 at double or more the normal data rate.
The C64 uses both phases of the 02 clock to access RAM. The clock is a 1MHz clock though so each phase has 500ns.
With 500 ns available it seems to me it should be possible to access the ram more than once during the half clock period.
The ram's in many C64's are 150 ns access time (Or about a 250 ns cycle time).
Using fast page mode access perhaps 3? bytes could be read in 1/2 cycle.

But I don't know what the propagation delays are like in the C64 or how tight the timing already is. For instance the cas signal travel through the PLA which has a propagation delay.

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I think Acorn's Electron does this, in an effort to save costs. It has just 4 DRAMs and always fetches or writes two nibbles in each access, in page mode. The CPU does this, and in the other half of the cycle the video logic does it. Sometimes the video needs more bandwidth and it stalls the CPU using RDY.

Don't know if this is helpful:
The C64 PLA has been dissected.

There is some text about timing and propagation delays starting at page 19 of this PDF:
http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c64/C64_PLA_Dissected.pdf