As an FYI, Jason Flynn over at Stardot has designed a small board with an LX9 FPGA and up to two 16-bit wide RAMs, and has taken enough orders to run up a batch of assembled boards.

The board is designed for use as a second processor to a BBC micro, but that means it has a byte wide memory mapped interface (at 5V) which should be suitable for any 8 bit host. Indeed, with different code the 40-pin connector could be rejigged to provide, for example, a serial connection instead.

Might be of interest to anyone to sign up for a second production run, or good as inspiration.

Of course, the 32-bit wide memory interface with 2 Mbyte of memory looks interesting from a 65Org24 or 65Org32 perspective. Or even a good old 65Org16!

See these threads:
http://stardot.org.uk/forums/viewtopic.php?f=3&t=9994 (Index/Signposts thread)
http://stardot.org.uk/forums/viewtopic.php?f=8&t=8932 (Order thread)
http://stardot.org.uk/forums/viewtopic. ... 780#p98780 (Tech thread)



Presently three types of CPU core are supported and tested (implemented in the FPGA):
"Matchbox sized 6502 / Z80 / 6809 Co Pro"
and there's interest in a PDP-11 core too.

It's only recently come to life, so no reports of very fast clock speeds yet.

Time has passed, so there are now reports of fast clock speeds:
- 32MHz 65C102 ( 64KB internal RAM, AlanD core)
- 112MHz Z80 ( 64KB internal RAM, NextZ80 core)
- 16Mhz 80286 (896KB external RAM, Zet core)
- 4MHz 6809 ( 64KB external RAM, SYS09 core)
- 16MHz 68000 ( 1MB external RAM, TG68 core)
- 32MHz PDP11 ( 64KB internal RAM, PDP2011 core)
- 32MHz ARM2 ( 2MB external RAM, Amber23 core)
- 32MHz 32016 ( 2MB external RAM, m32632 core)
(All of these cores can be held in one flash image, and selected at boot time under control of the 8-bit host port or the DIP switches.)

The large external RAM is 55nS access time, so that's good for operation at 16MHz.

You can buy the board here (but it's made infrequently in relatively small batches.)

(Edit: might be worth noting that the board acts as an 8-bit peripheral for a 2MHz bus. Its natural environment is the Tube connector which is standard on Acorn's BBC Micro and Master machines. There are also relatively easy ways to connect to the earlier Atom and the later Electron. But other hosts should be straightforward too, even non-6502 hosts. They will need some software to run the Tube protocol, or whatever protocol of your own which you might implement.)

In view of my own, earlier designs (for those interested, go to http://www.zeridajh.org/hardware/index.htm, Downloadable section), and the fact that Matchbox uses a 32 MHz oscillator (not a PLL as mine do), I'm somewhat curious about where the 112 MHz Z80 figure comes from ?

The fastest Z80 design in the Matchbox uses a Next-Z80 core clocked at 28MHz (which is generated from the external 32MHz oscillator using a DCM)

The CPI of the Next-Z80 core is ~4x better than the original Z80.

It's advertised as "112 MHz" based this, and on the results of running JGH's CLOCKSP BBC Basic benchmark:
- the "Combined Average" of the original 6MHz Acorn Z80 Second Processor was about 2.5MHz.
- the "Combined Average" of the 28MHz Next-Z80 was 46.56MHz

6 * 46.56 / 2.5 = 112 MHz.

See this post for the original numbers:
http://stardot.org.uk/forums/viewtopic. ... 30#p106301

(BTW: I don't actually have an original Z80 Second Processor, so I haven't confirmed myself that the baseline of 2.5MHz is correct. I'm happy to recalibrate if we can get better data.)

Dave

Wow. I didn't know the original Z80 was that inefficient. The 65C02 core I use eliminates a few cycles here and there, but nothing like that.

I'd still not expect advances in core efficiency to be worked into the 'clock speed' though. I'd expect a separate clock speed and 'benckmark speed'.

I think it's been a fair tradeoff - the benchmark speed is by far the more meaningful figure, especially given the experience with Z80 core differences.

As the design is open source, anyone really wanting to know the internal details can find it all there.

Sure. But that's why it's more fair to quote the benchmark separately and not suggest it actually runs at this made up clock speed. That serves only to confuse, since these coprocessor implementations are first and foremost a rebuild of existing hardware.

I'm sorry you were confused John, but I think the table does serve the purpose of telling people roughly what will happen when they use the copro.

Just trying to help improve the documentation, Ed. Keep your panties on.

Ah, tone is so difficult to render in text - I'm not annoyed! I acknowledge your observation about the speed, but I don't agree that it's worth making any change.

Come on. What kind of effort would it be to note the actual clock speed in the documentation. The real effort is in the benchmarked one. And if you document the latter for one coprocessor, don't you think you should be consistent and do it for all of them ? After all, most of the available processor cores have optimizations, there are differences in memory access speeds, all of these interact, etcetera.

Hi John,

I'm happy to extend the documentation with CLOCKSP benchmark figures if folk would find that interesting. I've made a note to do this, and to include the figures for the original hardware.

But in the Co Processor boot message there is only room for one number, and I wanted that to indicate the performance compared to the original hardware. Sometimes this is higher than the actual clock speed, sometimes it is lower.

For example, the 65C02 Co Processor is reported as 32MHz, even thought it is in fact clocked at 64MHz, due to effects of an additional pipeline register in the FPGA block RAM.

I'm interested in how you handle this issue in your 65C02 Soft Processor.
http://www.zeridajh.org/hardware/soft65 ... /index.htm
Are you using the external asynchronous static RAM at 50MHz? Were any wait states necessary?

Dave

Personally, I find the actual clock speed more important. I'd rather not have to dive into sources to find out such simple details. I'm less concerned about benchmarked clock speeds.


But that's not going to the core, right. So 32 would be accurate.


I use the internal RAM only. The way I wrote it in Verilog causes it to be synthesized as 'simple' dual ported block RAM with synchronous inputs (for read and write addresses and write data) and an asynchronous output (for read data).

I can confirm we measured 2.46 using CLOCKSP.

Thanks Ed.

Just one more thing. Can you confirm the Z80 was clocked at 6MHz?

There might be some out there that are slower - JGH reported his as 4MHz.

Dave