Hi

What is the best way of synchronising a higher clock rate to a lower one? I know the other way around would be straight-forward (to generate a 1MHz clock from a 10MHz one), but I need it the other way around.

I have looked into DS1077z-100 programmable clock in which the output can be switched on/off with a control pin. The problem is that there is nothing in the documentation that states whether the clock will actually start in the same phase (although I hope it will). It has a master clock of 100MHz, so to get 10MHz I will program it with a divider of 10.

Any recommendation would be appreciated.

There are many solutions on the market for problems of this nature. The ICS525 is one I've used myself, purchased from Digikey. It contains both a multiplier and divider, which in combination can produce all sorts of odd ratios.

Can you be more specific about what you're trying to accomplish? Perhaps one of the other ICS series chips would be more appropriate.

The adapter is a separate product, also from DK.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The external 1MHz input signal needs to be synchronised with the 10MHz internal clock so that they start approximately at the same time:

E.g. (each number represents a timeframe of 25ns):

CLK1 1111111111111111111100000000000000000000
CLK2 1100110011001100110011001100110011001100

Without synchronisation, the CLK2 would have a phase shift, e.g. it could start with a time difference of up to +/-50ns which is not wanted.

I need to synchronise these signals, then OR them (more or less like this):

CLK1 OR CLK2 = 1111111111111111111111001100110011001100

The issue being that I need a certain number of 0-1 transitions in the resulting signal.

A delay of 25ns on CLK2 would give:
CLK1 OR CLK2 = 1111111111111111111101100110011001100110

Which will give an extra 0-1 transition.

The search term you need, I think, is glitch free clock switching, or glitch free clock multiplexing. (You just might be able to avoid glitches by arranging the phase relationship carefully, but at a guess you'll either have a problem switching in, or switching out. There's no such thing as two perfectly synchronised clocks!)

The first couple of hits I got:
http://www.vlsi-world.com/content/view/64/47/
http://www.eetimes.com/document.asp?doc_id=1202359

Maybe so, in a case where the two clocks arrive independently from two different (and asynchronous) sources. But I'm unclear on whether that's the case here.

Input signal? Internal Clock? Am I right in supposing that the former is dictated to you, and the latter is a signal you generate yourself? I think your problem can be fully resolved without much difficulty. But I'm up past my bedtime, and trying to explain the details isn't a good idea at present

PS: it might be helpful if we know what you're actually doing. For example, is this a cycle-stealing scheme where a fast CPU and a slow CPU take turns sharing a single bus?

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

This is the fun part where you get to pore over datasheets for hours on end, alternatively hook up several different clock ICs to a scope and observe how they react in every possible variation of inputs.

Generally, you can't assume a thing. If the datasheet doesn't specify a particular relationship between input and output then the device is free to do whatever it wants. PLLs should, I would think, have the phases of the input and output clock synchronized, but there might be things going on (post dividers maybe?) that throw it off.

Here is one that does let you control the phase of the output explicitly via a synchronization input. That means you'll get a well defined relationship between the phase of the clocks. I haven't used it, just had the data sheet handy, there might be others that are much better, etc.

A PLL of some sort is likely required. I'm reminded of the 14046 ? CMOS PLL. A PLL needs an external divider circuit which acts to multiply the base frequency. PLL's have a lock time so some circuitry is likely required to hold reset active to devices until the PLL locks. Once it's locked the phase relationship between clocks is fairly constant.
I used a 4046 at one point running up to 6MHz (I think there are faster versions) to boost a 1MHz clock. Note there are PLL's built into most modern FPGA devices and they make it easy to manage clocks.

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http://www.finitron.ca

4046, that's a nice idea.

Suddenly, I feel reminded to the C64...
...where dot clock is generated from color clock by using a PLL.

The MC4044 phase detector used in the C64 probably is out of production,
but TI still sems to manufacture the 74LS629 VCO.

Related topic: "Clock-stretching circuits for slow peripherals"

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Wow. Lots of answers! Thank you for all the leads! I had to paint the porch before the weather and my wife started storming, so haven´t read them fully yet, but I will.

Anyway, the 1MHz is set and the 10MHz (internal) is generated by me. This is going to be part of my base computer for some time, so I want the principle to work. I forgot to point out that the 10MHz is not set. The DS1077z is programmable, so I may run it at 14MHz or overclock to 20MHz (depending on my luck and ground plane I guess). That is why I chose clock switching in the first post.

I will try to propose some solutions once I have read all the links.