Hello all,

In a recent lively discussion on the BBC Micro Mailing List the issue of high density floppy discs came up. I've managed to convince myself, if not the list, that an NMI service routine running at 2 MHz will be fast enough to do PIO (but only by making hefty sacrifices.)

The problem is none of the hardware was designed for HD data rates. When supplies of the Intel 8271 FDC dried up a lot of third party replacement daughterboards were made, all supporting DD MFM, until Acorn built the WD1770 into the B+ and later models.

My intention is to build a proof-of-concept to show HD is possible, to encourage the building of HD controllers (and also to disprove the critics ). I am fortunate to have a WD2791 based controller board, clocked at 1 MHz to give suitable stepping rates to 5.25" drives. However I'm reluctant to get the soldering iron out as things tend to stop working afterwards and I haven't seen this board often elsewhere.

The plan is to cut the track to pin 24 (CLK) of the WD2791 and wire it to pin 3 of the header (which would be the 2 MHz clock of the 8271). Then /ENMF and /5 can be attached to a spare 74LS74 latch on the board. This should mean my existing Disc Filing System will continue to work, but HD is available through user programs.

Pictures of the board type: front, back. Links to relevant datasheets are here.

My questions are,

• has anyone else seen this board (Opus EO 118);
• will pretending to have an 8" drive mean I can use HD 3.5" floppy discs;
• do you think this modification will ruin the board;
• besides wearing an earthing strap what can I do to stop killing my circuits?

Any help would be appreciated.

TIA

Greg

*crickets*

I'm sorry, this thread's a little off-topic I admit but the controller was a WDC design and I anticipated a little interest in upgrading storage capacity.

The modifications have been made, and the '91 will run at 2 or 1 MHz, confirmed by a seek test. Yet to determine whether this will actually give me access to HD floppies, when I connect a 3.5" drive I shall find out.

The 'spare' fourth latch was in fact the clock divider, so its input pin had to be cut and lifted. The latch now drives the two input pins as intended. It appears the circuit board was designed to accept any of the 279x series, hence the hard-wired divider. The inverting bus is going to squeeze timing badly.

Greg

Two things, really -- one, I think what you're talking about is *WAY* over the majority of this board's users heads (certainly mine at this point). Second, there are two WDCs -- Western Digital Corporation, and Western Design Center. The former is responsible for harddrive and other storage peripherals. The latter is responsible for CPUs.

This board is primarily interested in the latter; to the best of my knowledge, Western Design Center has never offered a magnetic storage controller of any kind in its history. Its product offerings always centered around its CPUs. I don't think anyone here really knows many details at all about the WD17** series of chips, let alone the interface details between HD and XD floppies.

If someone can prove me wrong, that'd be cool.