How is the instruction fetch handled?

[asm_2750]

I'm a little confused about how the 6502 handles an instruction fetch. It seems to use 3 bytes, to do a direct addressing instruction. The first byte fetched should the opcode, and the next location in memory is the address of where the operand is.

Now in a more detailed approach the PCs value is used to do a memory fetch and put the data into the IR. Then the PC should incrment by 1 to the operand addr and then do another memory fetch, then from there I assume PC gets incrmented by 1 again and the processor does the operation it is intended to do?

Does that sound right?

[8BIT]

I pulled the following from the WDC 65C02 datasheet. It give the cycle details for an absolute memory address mode.

Since the 6502 can address 2^16 bytes (65536), it takes two bytes to access any location in memory. So, an absolute address mode instruction requires 3 bytes: 1 for opcode and two for the memory location address.

The first cycle reads the opcode, the second cycle reads the low address byte, the third cycle reads the high address byte, and the fourth cycle reads the actual data from the location addressed.

Hope this helps!

Daryl

Code: Select all

1a. Absolute a
ADC, AND, BIT, CMP, CPX, CPY, EOR,
LDA, LDX, LDY, ORA, SBC, STA, STX,
STY, STZ
16 OpCodes, 3 bytes, 4&5 cycles

Cycle    VPB    MLB    SYNC    Address Bus    Data Bus    RWB
  1       1      1     1       PC             Opcode       1        
  2       1      1     0       PC+1           AAL          1
  3       1      1     0       PC+2           AAH          1
  4       1      1     0       AA             Data         1

[GARTHWILSON]

For further reading, you'll probably be interested in
http://www.6502.org/forum/viewtopic.php?t=621 and
http://www.6502.org/forum/viewtopic.php?t=594

[asm_2750]

Ok that makes alot more sense, thanks guys. I didnt know it took 4 cycles for a fetch, but then again, it is a 8 bit data bus. I've been working with a 32bit design for another processor the IR was big so the fetch from memory only needed to be done once. Now I can go back to designing my 8-bit accumlator machine in VHDL.

[kc5tja]

asm_2750 wrote:

Ok that makes alot more sense, thanks guys. I didnt know it took 4 cycles for a fetch, but then again, it is a 8 bit data bus. I've been working with a 32bit design for another processor the IR was big so the fetch from memory only needed to be done once. Now I can go back to designing my 8-bit accumlator machine in VHDL.

Well, technically, it takes only one cycle for the fetch. The problem is that the CPU, while pipelined, does not have any instruction cache nor even a prefetch queue. So it relies on RAM to hold all program information. This is why the 6502 and 65816 has no performance penalty for self-modifying code -- it's always fetching instructions fresh from memory.

As a result, you have 3 cycles for the instruction fetch, and then one cycle for the operand fetch (two for a 16-bit operand).

[asm_2750]

I guess I should have wrote my reply better. Yeah its one cycle for the fetch for the opcode, since the value is directly in memory, it should take an additional 3 to obtain the 16bit address of the operand(the second and thrid cycles since memory is addressed in bytes), and then get the operand value from memory(the fourth cycle). One thing tho, is the address for the operand stored in a hidden register(i.e. a register the user cannot touch and is only used in fetching?). Eh, I bet I still replied wrong, but what I said seems to make sense to me. On the topic of pipelines, if the 6502 is pipelined, how many are there?

[GARTHWILSON]

> On the topic of pipelines, if the 6502 is pipelined, how many
> are there?

The only pipelining is what is described in one of the links above-- that the processor can be doing more that one operation per clock so an individual instruction comprised of several steps can execute in fewer clocks, and an instruction is often finished up while the next opcode is being fetched. IOW, there's only a one-clock overlap of instructions, and not on all instructions. A "store" instruction for example cannot do its storing while the next op code is being fetched, since the buses cannot be used for two things at the same time.