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I was surprised that you used nand gates to decode all the ICs in the Bench-1 illustrations. Please I need some tutorials on this nand gate decoding process. For example, you chose Address A8 and /A8 to separate my two VIAs. Why did you choose A8 and not A7 or A9 or any of the other addresses?
The A8 and A8\ was only for your wanting to put the two VIAs at addresses $100 apart. Using your '138, you'll use the top three address lines to get the A000-BFFF address space; but the $100 is selected with A8. Similarly, a $80 difference would be selected by A7, $40 by A6, etc.. Even if you still want to use your '138 and have your VIAs on Y5\, you really would not need the inverter to select one VIA when A8 is high and the other is low. To simplify, you could just connect one VIA's CS1 to, say, A7, and the other VIA's CS1 to A8, and omit the inverter. Then the base addresses would be $A080 and $A100. If for some unusual reason you wanted to write the same data to both VIAs at once, like to set them both up the same way or start their timers simultaneously, you would write to $A180+the register number.
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Could you please use your illustrations in Bench-1 to further explain to me.
It uses A15 to select between ROM and everything else. That leaves 32KB of ROM space, regardless of whether or not you use it all. You could still do it this way for an 8Kx8 or a 2Kx8 ROM for example.
If it's not ROM, it uses A14 to select between RAM and I/O. If it's RAM, it gates it with phase 2. The scheme leaves 16KB available for RAM. In my case, I needed more ROM than RAM, so I have a 32KB ROM, but I'm only using half of a 32KB RAM (since commonly available RAM ICs jump from 8KB to 32KB, skipping the 16KB). With a small change, you could get 16KB of ROM and 32KB of RAM.
If A15 and A14 point to the I/O space and all the common I/O ICs have two select lines, you use the next address lines, one to each IC, to select which I/O IC you want to address, leaving just enough at the bottom for the register selects. The 6532 RIOT needs 7 or 8 register-select lines IIRC, but there's not much sense in using a 6532 if you have 6522's and separate RAM available. The 6522's need 4 register-select lines and the 6551's need even fewer (2); so if you use A0-A3 for register selects, all the address lines between A3 and A14 (non-inclusive) can be used for chip selects. That's ten.
I hope this is clear. It is common for newcomers to make the glue logic much more complex than it needs to be, requiring more board space, more time to build, and longer total propagation delays which limit the maximum speeds.