It's not a "false write cycle." WDC makes no guarantee as to what is on D0-D7 when VDA || VPA is false, which means your hardware should not be following RWB during such cycles in an instruction.

If you are designing a system around the '816 it is incumbent that you account for the MPU's characteristics. That means when VDA || VPA is false no chip selects should be asserted, as there is no guarantee as to what is present on A0-A15, or what is on D0-D7 when Ø2 is low, which is when D0-D7 becomes A16-A23. This can be especially important with I/O hardware accesses, which could trigger unintended behavior in some devices.

VDA and VPA qualify all bus cycles, as well as the control outputs E, MX and RWB. Ergo the state of RWB is meaningless when VDA || VPA is false. This applies regardless of which mode in which the '816 is being operated.

Have you read the 65C816 instruction operation table starting at page 38 in the data sheet? It explains all of this in considerable detail. The Caveats section on page 51 sheds additional light on how the '816 operates.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Can you cite a reference for the E and MX part of this, BDD?

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I can't specifically point to MX but I did observe back when I was first operating POC 1.0 in emulation mode that E was not constantly high, even though the top of the reset code was:

Code:

         sei                   ;IRQs off
         cld                   ;ensure binary mode
         sec                   ;ensure...
         xce                   ;emulation mode

   ...etc...

At first blush, it would seem that E should go high when XCE is executed and stay there. However, that wasn't the case and I surmised that E was not being driven during the intermediate bus cycles when VDA and VPA are both low. I further surmised that was probably the case as well for MX, which also has to be qualified by Ø2 and hence would have been difficult to observe with the test setup I had at the time.

So, this observation was casual in nature, as I had (still don't) no specific plans to use E and/or MX for anything. Also, around that time, my old Beckman scope was on its way out and the second channel had completely quit, so I didn't get around to comparing E's status with VDA and VPA. I was well on my way to getting POC V1.0 to run in native mode, so I didn't give it any more investigation.

I'm sure my statement is worthy of a challenge, but the more I work with the '816 the more I realize how important VDA/VPA qualification is to stable operation.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

@BDD -- thanks for clarifying. Turns out we agree the point you made about E and MX is challenge-worthy. The experiment to explore it remains incomplete, there's nothing in the datasheet to support it, and we agree it's an unlikely-seeming thing in the first place.

An easy mistake to make. (And I don't mind surmise when it's identified as such.) But datasheet timing diagram Figure 4-1 shows that neither E nor MX can be "qualified by Ø2" in the usual sense.

-- Jeff

[ Edits ]

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html