I meant to add here today, as I have been studying memory pretty seriously this past one or two months. Much more effort must go into it, and I am out of time for posting things today. maybe this weekend or next week, I can update on my "counters + DPRAM + FIFO? + Bus switch" idea.

I am seriously considering PSRAM after the DPRAM, until I can RAID array the raw video data.

IDT Quickswitch seems best. The image sensor I use have some useful synchronization signals on the digital video output bus/port. VERY Useful!

Must also review master and slave mode for these image sensors. Their use in synchronization of the system could be invaluable.

So, today I think I should post a small piece about my thoughts for "Memory Architecture for a Focal Surface Array Computer Utilizing the 6502-family Microprocessor". As is usually the case, I will be "hacking it", but this time, doing so with more "specifics" than usual.

My one or two month hiatus from these pages was an introspective recognition--an admission--of my "lack of depth" on this issue. Specifically, I needed to know (1) the types of memory available and their capacity, speeds/frequencies, fundamental unit cell, interface, purchase price, etc. (2) Bus switch characteristics, available products, prices, speeds, fundamental architecture, etc. (3) Timer-counter prices, availability, prices, speeds/frequencies/delays, and/or (4) necessity or non-necessity of DMA or other memory controllers, (5) interface to large storage and/or long term storage.

Driving all of these questions was my need to deal with large amounts of video data, quickly and efficiently (i.e. VGA, 12 bit (1.5 Byte) per pixel X 488 X 648 X 30 fps X 12 sensor array (6 per eye) X 60 sec/min X 60 min/hr X 16 waking hrs/day X 365.25 days/year X 75 years (robotic-humanoid average lifespan). In essence, 6 sensors at VGA is really only a 2 megapixel camera, X two eyes, is 4 megapixels. 30 frames per second is a decently "humanoid value" (i.e. according to Hugh Davson's "Physiology of the Eye", a reputable authority on the subject, the flicker fusion frequency, depending upon experimental assumptions and characteristics, hovers between 40 and 60 cycles per second). So, 269 Petabytes is the lifetime of raw video data for my robot. I have researched a few RAID arrays whose capacities approach that "regime", i.e. the "PB regime". Also I have perused a few brief descriptions of SATA (which, I will probably need, though perhaps thunderbolt might be a "new standard" to consider?). One extremely important point to consider, is that, for human-like intelligence, one does not need "perfect recall". In fact, such perfect recall would probably be detrimental to the proper functioning of a "Human-like Artificially Intelligent Robot".

Now, why 6502? Because I have a history with the processor, albeit, a cursory and somewhat emotional/nostalgic attachment. Secondly, it is accessible in a way that "new" technology, generally, is not. Thirdly, while it is a wholly inappropriate tool to use for the vision tasks that I expect to tackle, it might be an adequate (1) memory controller, i.e. for switching the bus between the various elements of the system, and (2) it might even be programmed to be the "voice chip" (a late realization I have come to, after tackling the "speakjet" magnevation chip, for a week or two!). I read a rumor, somewhere on the internet, that the speakjet is just a "pre-programmed PIC", but I think the author was confusing it with the BASIC Stamp? (If any of you out there in 6502-land know for sure, do let me know!). The Stamp is definitely a PIC, and though I bought the dang thing some ten or so years ago, I didn't find it a very interesting or insightful description of how a microprocessor works. I think, perhaps, it might teach BASIC language, but probably obscures more about microprocessors than it actually teaches. The book that came with it is useless, but one only learns this after one has downloaded the pdf manual with extensive documentation of how the BASIC Stamp really works (i.e. it works like a PIC!)!

Perhaps a multiprocessor 6502-system is what I should envision? OK, enough with the preliminary discussion. Let me launch into some concrete part numbers that I have been "mulling over". So for (1) counters, (2) Bus Switches, (3) FIFO/DPRAM, (4)?Intermediate storage?, (5) Permanent/Semi-permanent Storage, (6) RAID/MAID Permanent Storage, perhaps the following would serve admirably and/or suffice?

(1) Still researching (due to my concerns about propagation/gate delay/ripple/etc.). Have ordered a book on the subject from a college library, though I might be able to ferret one out on the internet (Some international scoff-laws think that scientific knowledge should be FREELY available! Imagine that! What a novel idea! Certainly not anything that people, like, have fought wars over, or anything silly like that! (sarcasm!)). I am settling on synchronous counters, obviously, but still don't know enough about counter construction and/or market availability to make a decision. One page that I went to recommended Xilinx products (interesting history to that company; a few executives spun off/out-of Zilog, itself a creation of Faggin!), but these appear to be PLDs and FPGAs and such. The original Kodak documentation (for my image sensors) indicated Altera, their (or "one of their") chief competitors in the FPGA/PLD market. I consider this overkill, for a mere "counter"; but I could be wrong. I lean towards synchronous counter, naturally, as asynchronous will "ripple" and have large delays, inadequate, I presume/assume to the proper completion of the task of timing transitions in a memory management/bus system.

(2) IDT QUICKSWITCH IDTQS32XVH384 (20 bit bus switch; no delay? can this be true? About a $1.50, or so.). Also of note, though less studied by me, was Crosspoint Buses/Crosspoint Switches. This, it should be noted, can be a confusing terminology since "crossbar" is also a term in computer science. I think it was TI that offered crosspoint switches on digikey? They were slightly more expensive, so I only ordered one, and have barely perused the documentation. (there is an article/blurb about the terminology confusion on this fine website! http://thememoryguy.com/ . Also, note the recent promise/peril of the 1-transistor SRAM cell! While we heard rumors of this semiconductor species before, it never came to fruition. A new company thinks that they can do it! I guess we'll see!). ( http://thememoryguy.com/crossbar-or-crosspoint/ ).

(3)I am settling on AverLogic AL460A; or one of their similar offerings. This FIFO is the largest capacity I could find (at least, largest for under a hundred bucks). I suppose a 20 or 30 $ chip is nothing to sneeze at (especially if one has a tendency to break chips!). Texas instruments had a good/cheap FIFO (several hundred KB, 20 or 30 bucks?), and there was a Dual Port RAM from IDT (only 1 KB, but also only 10 bucks, approx.). There are options here, so I think I can be flexible, for now. AverLogic is a fabless-semi company, and they are advertising a new roll out ?soon? of a 32 MB FIFO, largest in the industry! I am just hoping to get my hands on a 16MB chip.

(4)? Intermediate Storage? Where should I shuttle all the information from the FIFO/DPRAM to? It needs to be large capacity, to deal with the inherent high bandwidth of the optical world i.e. video sensors. This would seem to limit us to two choices, SDRAM (DDR3 or DDR4) and/or Flash (EEPROM, NAND?) chips. I have ruled out SDRAM, provisionally, since I have little hope of interfacing to these devices, at my present level of knowledge. Though, perhaps, were I to purchase some DIMM sockets with SDRAM already on it, then I think I could tackle the SATA interface. So, that remains an option. (Note: on all discussions in this post, you should note that I have not worried about logic levels and/or power levels for the various technologies, assuming, that if there is some "sticking point" on this issue, that some solution can be easily implemented. Safe assumption? I dunno? Its a gamble.).

Would a FIFO or DPRAM be able to feed some SATA interface, and shove the data directly to a RAID array? Maybe. This seems appealing, but, I think, unlikely. Maybe there is some such thing as a "SATA controller" (IC?) that would do this? The data coming out of each image sensor chip is 33-to-45 MHz, 12 parallel bits (or "lines" or "traces"), and a pclk, hsync, and vsync trace. The latter three traces area available for driving counter circuits, and are programmable for rising or falling edge synchronization of the valid pixel data (i.e. synchronization with the memory chips that will receive said data). I see no problem getting the data into the FIFO and/or DPRAM, and back out of it again, but getting it into a larger capacity chip (on the order of GB) is priority, as no FIFO/DPRAM is that large, and the KBs and MBs "fill up quickly").

I looked at PSRAM (pseudo-static/Page RAM; actually a DRAM pretending to be an SRAM) briefly, but it is still in the low MBs regime, and GBs are what I am looking for. Of course, there is "data compression" and over time, even, "data discard", but the industry is certainly ready and able to do the things I envision. A 1 Petabyte (expandable to 4 PB, or so) RAID array exists, and can be bought for just a mere half million! (Other solutions offer a quarter PB, for far less, though populating the bare-rack array with the individual 6, or 8, or 10 TB SATA spinning platter HDDs is also an expensive proposition.). One should note that human biology is curious and applicable here; specifically some sort of implementation of the optic chiasm would be advisable. This, in addition to my original intention of a foveated image sensor (before I adopted the strategy of the "foveated, curved, focal surface array, Multichip module" concept) and in addition to implementations of binocular fusion and stereopsis, might--and probably would--result in further reduction of the size of the data. But this would require significant computation to achieve. This "intermediate storage" is probably a necessary step, since, any binocular fusion, and its attending data reduction, would best be implemented here, in "real time". (Note: I still consider the PSRAM, because, the interface is easy, just like SRAM; but unlike SRAM the densities are larger; i.e. low MBs regime.)

Some commentators--of an earlier age--have considered Strong AI to be out of the reach of computer scientists (Metamagical Themas? Douglas Hofstadter? I think? circa 1980s.), since it takes a mere 200 ms from the moment an image is introduced to a human subject to the moment when the person recognizes and identifies the image. In our present age, to a modern computer scientist, 200 ms might seem a lifetime. However, it does bear mentioning that sincere effort spent achieving this goal of quick image recognition is still a necessity, and it will not come easily or naturally. In short, much engineering will be necessary to achieve that goal.

And so, with the AverLogic chip I mentioned, reaching into the low MBs regime, the PSRAM seems less likely or necessary. And so, either a DRAM DIMM (Samsung has some in 128GB and possibly more), a 256 GB chip (Samsung made for mobile applications? Flash, I think?), a 512 GB (Flash?) SanDisk memory card, or some Flash EEPROM chips seem wisest, for intermediate memory. I know SDRAM (DDRs) are the "workhorse" of the industry (circa 1990s to now), but my "needs/wants" might be different from those of "the industry".

I am actually leaning, most, towards individual Flash chips, of 1 to 4 to 8 GB capacity (I think those were my options for capacity? And they seemed fairly cheap. Interface could be difficult; I shall read more about it. It might be possible to pick up a "kit" that advertises a FIFO to Flash/USB interface, and I will research that next.

(5) Once I learn SATA, it should be pretty straightforward to use spinning platter disks, or SSDs, or even Blue-Ray (MAID array? Massive Array of Idle Disks?) + cheap-ebay-purchased-Jukebox. The "memory guy" has a good article/graph about price per bit, over the past 2 decades. He still lists spinning platters as the standard and economical choice, though 2013-2014 had a slowdown in the decreasing price per bit trend. Also, I found a link, or two, to a Western Digital 10 TB, helium filled (to reduce friction, and thus, increase efficiency) HDD. I Think RAIDs are evolving too. With more platters the failure rate increases, and the redundancy might not be adequate to recover the information (i.e. if two disks fail simultaneously, it could spell trouble, as the data from the second disk must be used to reconstruct the data from the first.). I have seen some RAIDs with slots for SSDs and some for HDDs. Perhaps this is the best solution? SSDs, I gather, have reduced failure rates, and HDDs are cheaper per bit. So, the SSDs could back-up the HDDs.

(6) So, this item is not all that different from item (5), since both (5) and (6) will rely upon what I do in item (4) (i.e. still "indistinct"). So, why list a separate (6)? Because, I just wanted to comment and reiterate that RAID and/or MAID arrays are envisioned. The "mobile robot" should not have a "weighty" memory, as it must be "achin' and quaking and shakin', like humans do"--to paraphrase David Byrne of the Talking Heads. (As I write, I am in the public library, and some toddler, here, is presently giving her mother a "run for her money". Funny where "inspiration-to-write-and-design-and-engineer-and-create" comes from?). Downloads every night to the RAID/MAID structure are envisioned, and even a "dream state" might take place.

Now how about that? Do androids dream of electric sheep? I suppose I could write a specific program and introduce it periodically (like my own recurring dream of the ocean and waves and the sand running between my toes). But I digress. What companies make large RAID arrays? Well, even a small one of, say 32TB, might be useful to me. The empty rack can be bought for 65 to 100$, and populated with disks later. Buffalo (also maker of B-RAY drives), Synology, Rosewill, CineRaid, and GSpeedQ seem to be the small RAIDs that I have listed in my notes; they seem to be not-too-small and somewhat affordable. I think I have SansDigital listed as a supplier of medium sized, affordable RAIDs, though I see one or two offerings that I would call "Big" (i.e. 100TB or more). Finally, I found two suppliers of "Petabyte"--or fractionally so--regime arrays; PBRAID array (i.e. Nomadic PB) and Aberdeen (1/2 mill $, in 2012!). I also have listed a supplier of DIMMs (SDRAMs) called Dominator Platinum (Corsair), but I somewhat distrusted their flashy packaging. No matter; I have no "money to play with" anyway, so I will look beyond much of the packaging and find the "value" when I finally purchase something!

Those are my thoughts for today. One hopes that tomorrow will be more "reduced-to-practice" than today was! Cheers!

P.S. In summation, I might reduce the 6502 to mere "accessory controller", i.e. "memory manager", but I still like the idea of mere "phoneme/morpheme concatenation" being driven by this simple, elegant, fast, and historically YUGE (via Bernie, not Donald!) computer chip. As for video processing; that is another beast entirely! DSP! Yes! I'll cross that bridge when my knowledge, skills, and abilities allow it!

P.P.S. A serious question, to any who can answer. How many memory chips can be simultaneously driven by one image sensor? How many "Intermediate chips " (i.e. SDRAMs, Flash EEPROM NANDs, etc.) can simultaneously be driven by the output of a FIFO and/or DPRAM? It might be nice to have a bus that can branch to two memory devices and feed them simultaneously? Pipe dreams?

For humans, our peripheral vision's resolution is not nearly what it is at the center. The peripheral seems to be mostly for sensing changes that might prompt us to look in that direction, or only keep an awareness of what's over there, in less detail. From there, the eye muscles keep working to point the eyes to where we need the most detail. There's probably something there to learn from and benefit from that could dramatically reduce your storage needs.


With CMOS, the fan-out is dependent on almost nothing but the speed. CMOS's input leakage current in on the order of picoamps or femtoamps or something like that, so the only load they present to a driver is the capacitance (a few pF for each input) that needs to be charged up.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

That's something with which I have become acutelyy aware since my left eye surgery in December. The left eye's peripheral vision is good, while its central vision is not.


In most of the stuff we do, parasitic capacitance in the circuit "infrastructure" will be much more a factor in ultimate fanout (and speed) than any leakage in CMOS device inputs. As has been demonstrated many times, a properly constructed wire-wrapped unit can be run quite fast (Cray-I was wire-wrapped and ran at 80 MHz, if I correctly recall). A good PCB layout will readily support the maximum speeds at which discrete W65Cxx devices can be reliably run.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks for the comments. I will cogitate.

Purchasing a FIFO chip today. AverLogic, AL460A (16 MB). I hope its a good choice? I checked the pdf/schematics and it claims to be easy to implement. It appears to be so.

Bummed about the Flash chip I was considering. While the 12 bit output of the image sensor has a (few) synchronous signal (s) to keep things "synched", the aforementioned FIFO is 16 bit wide (leading to, effectively 12 MB total, unless I get fancy, and "wrap around" the extra bits---which I have no intention of doing), and the Toshiba (32 Gb) chip is only 8 bits wide. Also, The Toshiba FLASH has no address pins (despite the package having numerous/innumerable "NC" pins!!!! Maddening, that it could have been easier!)! Multiplexed I/O pins 0-7! Five cycles, just to input one address!

So, I might shop around before I settle on an "intermediate" storage element/chip (i.e. "GB regime"). SATA is probably the next big "learning goal", for me.

Your comments triggered a few (non-electronics) thoughts. I will try to post a page or two (scanned/photocopied) of the books/papers I mention in this next paragraph, as they are probably important works. Binocular fusion/Stereoacuity can also reduce bandwidth (as alluded to in my post, above). Also, computer science knows more than a little bit about video compression; I will, at some point , consult such work as has been done there (VGA and/or HDTV signals and standards, seem most relevant).

Much interesting work on the human eye was done at Dartmouth, circa 1900-1950, at the Dartmouth Eye Institute (now defunct and/or rolled into the med school, there). I mention Ames and Proctor, Kenneth Ogle, Rudolph Luneberg, G.H. Gliddon, Harry Edwin Burton, and Brian O'Brien (Rochester, NY; same period), among others. JOSA (Journal of the Optical Society of America) was a common repository for their collected/published knowledge. Burton did the first English translation of Euclid's "Optics", circa 1945, but died before it was published (before that it was available in Ancient Greek and Latin--and ?German?). A colleague finished it, and published in JOSA. Lunenberg was an interesting character; he claimed that visual space was Non-Euclidean, a claim that I consider to be, at worst, dubious, or, at best, true but irrelevant (He did tend towards the opinion that Object Space is Euclidean and Image Space is Euclidean, but the "mental transform" to Visual Space, was a Non-Euclidean one. What this could possibly mean, especially in an Einstein-ian Universe of "Possibly Non-Euclidean Space-Time" is anybody's guess. I regard Non-Euclidean geometries with skepticism, but I am in the minority on this point; possibly enjoying the company of merely Charles Dodgson, and few other serious, indisputable intellects.).

Osterberg (Swedish?Finnish?Danish?), Alvar Gullstrand (of Nobel fame), and Ramon y Cajal are Europeans whose work must be mentioned here. Osterberg's retinal cell count of 120 million (approx.) rod cells and approx 5 million cone cells was the accepted figure for roughly 60 years. Nobody has ever counted all of the retinal cells, as such a task would be next to imnpossible, and inefficient in man hours. Statistical samples are adequate. In the 1990s Curcio et. al (Neurology Journal? I forget the reference?), used a computer to do the counting and they were able to get a larger sample size and, presumably, more accurate counts; 90 million rod cells and 6 million cone cells. You'll note my mere "1 megapixel (2 Mp total) binocular array" is much less than this, and is already significantly "multiplexed" and/or "pooled data"/"data compressed". It is a "hardware compression". It is also compensation for the fact that I don't have a semiconductor factory in my back yard (though I won't rule out, someday, building one! The Hubris!). Gullstrand's figures for the dioptrics of the human eye won him a Nobel Prize and, presumably, were used for G.H. Gliddon's scale functional model (manufactured by Goerz Optical, US branch, New York, circa 1920s). Gliddon lacked the proper optical materials (I have a pdf of a US army (navy?) procurement report indicating that pre WWI the nation was deficient in its "glass studies", compared to the Old world. This is, perhaps, not surprising, since the nascent photographic science, arising in the 1820s-1840s, only drove systematic designs for photographic lenses through the 1860s, and thus, the need for new glasses, in the 1870s-1900, via the Jena, Schott/Abbe/Zeiss partnership (i.e. division of labor).) to make a truly 1:1 object to image ratio, and in any event, it is not known if he placed a curved "retinal field" as target. My analysis and review of Gliddon's work can only be considered cursory and incomplete (apologies!). Nowadays, the experiment could easily be repeated with fused silica, CaF2, MgF, or LiF (though birefringent properties of crystals might show preference to the former two). Finally, Cajal's adoption of Golgi staining (with silver crystals) allowed the furtherance of the neuron theory (another Nobel winner! This one to "the shoemaker's apprentice", Cajal!), without which, no real knowledge of the retina would have been possible. (Maybe I overstate the case? The knowledge of rods and cones goes back a bit further; I think, for such a discussion, one would consult "Natural History of Vision" by David Wade? The name "Treviranus" sticks out in my head? "Regimontanus"? I forget?).

Well, that is good for today. Much about this project seems historical and monumental; but I am mere mortal. I have dusted off my "LASI7" IC layout program, my "OSLO; student version" (Lens Design) and an old copy of Meyer and Grey (Gray?) "Analog VLSI Design" (or some such title?), so my "focal surface array" might someday be "high-fallutin''" science. For now, it is just a "hack", with a new FIFO, and a "not-quite-adequate-FLASH-GB-chip". Cheers!

Haven't added here much, lately. Still thinking and working, but not much intelligent to say (not that it stopped me before!).

I am a bit perturbed by the inaccessibility of Flash memory stuff. Seems (a) complicated, (b) not made easier by lack of documentation. Maybe its my imagination?

Some folks out there are trying to keep USB standards open and free (most developers are encouraged?/required? to give 5000$ if they are going to developed USB products? I dunno? I think "hardware hacks" should be easy enough?).

So USB and SATA will be known to me in the very near future. Most USB is four conductors, I gather?! Awesome to see that "twisted pair" is involved! An old standard; telephone! Telegraph? I think? Differential signalling is not entirely understandable to me, yet. Lots of "Js" and "Ks", without out much discernible pattern (to my mind; yet!).

So, a brief synopsis of my mind is this; KAC-9628 CMOS imager (12 bit output and one pclk (and hsync and vsync too)) will feed the AverLogic 16 MB FIFO (16 bit input and 16 bit output; I might leave 4 bits empty! But it seems like a waste!), and then AL460 outputs the 12 data lines to a FIFO to USB converter (I am thinking FTDI's FT600/FT601; though they have about ten or so products that might be suitable, and I have a schematic from somebody else's online project that utilizes the FT245RD (I think that's the number?), so maybe I'll use that one?) and taking the USB 3.0 signal out of the FTDI chip, I can feed it to the SM325QX [Silicon Motion Inc.] (or some similar chip; again there are about ten choices and I have little way of knowing which is the best one for a newbie!). (NOTE: USB 3.0 has 6 signal wires, I gather? Three sets of 2; three differential signal "twisted pairs", I think?)

Here is where the good news starts. After obtaining a USB signal and a USB controller, like SM325QX, one only needs some flash memory chips and voila! Gigabytes of uncompressed video memory. Gigabytes of raw data for a data-greedy scientist like me to play with! Hooray! Convoluted? Well, just you wait until I break out the DSPs and start deconvoluting (hahahah! That was a computer science/imaging science pun!). The REALLY good news is, I had some old broken flash drives hanging around, and so I opened them up to see what made them tick. Just two chips; A Micron Flash NAND and a Silicon Motion Flash controller. Besides that, about ten resistors and/or capacitors (indiscernible) and probably 3 to 7 layers of PCB (curse you, blind vias!). One lonely little LED. I didn't know they made them that small!

And so, anyhoo, I am also looking at the Cypress CYC768033/34 (EZ USB to Flash memory), but it might not be right for the project, and it might be too expensive (at 13$, whereas Silicon motion is just 3$ or so). One other part that keeps slipping my mind is an NXP part (SDIO101AIHRZ); I should print the datasheet and/or read it.

Bad news, of course, is the fine line PCB and multilayer stuff take sit out of the "hobbyist realm" again. But let's face it. I was always headed there, anyway! Maybe I need to get some HDL programs and/or Verilog programs and/or hit the Wakerly textbook HARD! Then leave the "fab stuff" to the "fab guys"? But where is the fun in that!

So, contemplating buying some prepreg and setting up a surface with "pilot holes" i.e. "registration holes"; Maybe I'll go multi-layer after all. Finally going to take BDD's suggestion and get a real PCB editor. The one I dl-ed and started working with had a 300 pin limit! What the heck is that! Three chips into my design and I have to stop cuz the freebie (was it DIPTRACE? I think?) software got finicky! Beggars aren't choosers, but when free and good software is available, I will find it and use it. Cheers. Thanks for following my meandering brain!

P.S. Have read a few things about the flash memory market online. A couple years back a big anti-trust suit and price fixing scandals and such. I didn't go in depth into it, but I even heard/read some rumbling that the flash controller market was involved in some fierce competition and/or litigation? Oh well. Not enough room in my head for such things! Suffice it to say, I was glad to find the wikipedia page that listed the independent supplier of flash memory controllers, so that I didn't accidentally design around something that was part of somebody else's "vertically integrated, cash-cow, supply chain"!

P.P.S. I haven't worked out all the (a) frequency requirements, (b) power requirements, (c) logic level requirements of the above devices, but some of them are obviously a "good fit". I suppose, lots of homework left to do! but at least it is starting to seem possible to deal with high bandwidth (i.e. raw video data).

Neato; telegraph was not twisted pair. https://en.wikipedia.org/wiki/Twisted_pair#History

OK, having fun with this article; but in need of dinner. You guys can try this refresher course, if you want to!
https://en.wikipedia.org/wiki/Balanced_line

OK, maybe its easier than I have been making it? Maybe I could skip the FIFO altogether? I think FTDI had some "parallel to USB" converters? Could the 12 bits (parallel video data bus with synchronous pclk) of the KAC-9628, 48 MHz feed such a converter, which would feed a USB signal to the SM325 and thus the Flash NAND? I dunno. its getting late and dinner is seriously overdue. Cheers!

Still no "closure" on my plan. Here is a fella describing flash NAND and difficulties in reverse engineering (nevermind engineering!). http://joshuawise.com/projects/ndfslave . I guess it is "do-able". Considering walking back my plan to NOR Flash, but not sure that will be any easier (even though Joshua wise says it is!).

Just thought I'd pop on the forum here today and search to see if anybody here has dabbled in FLASH NAND. I suppose it might be out of the purview of the average 6502 project, but sinjce I am contemplating some USB connection, maybe some info on "USB hosting" and/or ONFi (Flash open source organization) is here? Cheers.

Looks like you have quite a project brewing. A vision system of sorts. I wouldn't mind learning more about computer vision, I gather large parts of it have been solved recently.

I just wanted to mention that FLASH chips typically have a limited number of write cycles (although it might be large eg 100,000+) So they are more suitable to permanent storage rather than as temporary cache type devices. They don't have the same use as random access memories like drams. The image sensor output could be going to a massive flash memory (270 Peta bytes?), but I'm assuming there would be some sort of intermediate processing taking place. To reduce the amount of memory required and to simplify the interface to other parts of the system. FLASH memory I think may also be slow for memory writes. I think you mentioned something like 44 MB/s required ? That's about 20ns for a write cycle. Although the memory could be interleaved.

Looking forward to reading more posts.

_________________
http://www.finitron.ca

Thanks, I think I am alright on the Flash cycles. (If not, I might be daft enough to just chuck the old flash when I'm done with it, and add some new ones!). Is memory THAT cheap? RAID arrays are probably best, but I don't know SATA yet. Probably need some DIMMs too!

My silicon motion (flash controller; mostly SM3257EN, but I purchased other types too!) chips don't have a data sheet; its like flying blind. The wholesaler just has the brochure and that seems to be all that silicon motion offers too. I found a Russian website and a Spanish website indicating how to hack them--once your flash drive is broken or partially broken--but have found almost no genuine information on how to proceed.

What part of vision are "solved"? I know these iphone/pads are nifty things, and maybe even the 3-D, never-focus, "all depths pictured at once"-type things too, but there is, as always, alot of hype in the industry. It is hard to know what will be the "next thing". I remember a few years back everything was going to be "Motionless mirror-less Non Prism -something or other" SLRs--medium quality cameras for the amateur-professional market. two sensors; one for the viewfinder image and one for taking the picture. TTL; mirrorless Through-The-Lens technology. I am not sure it ever panned out (but I am out of the "consumer" loop. I just design the stuff--and poorly, at that, so far--I didn't say I could afford any of it!).

Occasionally in SPIE or IEEE, or just, generally, on the web, I run into papers discussing the military's desire to use vision science to pick out objects that are threats from the background or from non-threats. This disgusts me, mildly, so I rarely read them.

I just got my "USB Complete" by Jan Axelson, in the mail today. Good book. I probably could have "hacked it" with the information from the USB standards organization, but some of the "leg work" is done if I use Jan Axelson's books. This one was cheap (4$) but I have another coming because it is out of date (i.e. copyright/printing circa 2001). I think the other one I ordered is titled "USB for Embedded designs/applications", same author. 7$ or so.

1969 was the first image sensor. Before that it was image tubes. Vidicon, plumbicon, etc. James Janesick has an interesting book, "Scientific Charge Coupled Devices" (copyright 2001, or thereabouts) giving the physics and function of CCDs. CMOS sensors have been challenging CCDs these past 15 years. Nobel prize was given to Boyle and Smith, circa 2007, for their Bell labs patent/invention of the CCD. Janesick, like a modern day Galileo, was the first to point one at a planet and take a picture.

I read alot, and I like history, Euclid and stuff. Jay Enoch has a paper about mayan lenses in SA, and an even better paper about Le Scribe Accropi. The seated scribe was an Egyptian statue guarding a pharoah's tomb. It had lenses built into it--presumably to ward off tomb raiders with a flash of their own torch reflect from a "copper retina". Reminded me, almost, of Kodak and IBM applying copper process to their image sensors (instead of the old aluminum and/or polysilicon wires). In some ways, I seek the sort of adventure that the ancient sculptor sought, but when I tell people around my sleepy little (politically treacherous!) hometown, people give me blank stares and suggest we go to a monster truck rally instead. Hard to see, once you have a good idea, how others can be so blind to it? Oh well. "The soi-ch [search] continues!".

SPIE (society of photometric instrumentation engineers) has some "yellow books", i.e. Proceedings, printed that are all about Focal Plane Arrays, which sounded like exactly what I wanted to do, only they seemed to center on IR sensors and/or optics (weird glasses like chalcogenide and such!). So, I kind of want a "foveated focal surface array" or better yet, a "retinomorphic foveated focal surface array" or a "anthropomorphic foveated focal surface array". I don't have a Semiconductor fab in my back pocket, so I figured I would "butt" some market bought devices. The process has been painstakingly slow, moistly due to other people's lack of interest and my lack of funds.

Janesick had a few pictures and mentioned abutted arrays, but he offers the reference and then doesn't dwell on it too long. I have seen a few good pics of abutted CCD arrays--usually NASA--on the internet, and I might even have posted a few links to them within this forum, somewhere. What has any of this got to do with 6502? Nothing at the moment, but I swear I am getting back to it. I have to work backwards from the new technology, and slip in the old where I can.

That is kind of why I am skulking around these pages today. I remembered reading about 6502-USB implementation, and I wondered what that looked like, now that I know a little bit. I'll bet 6502 can't be a USB host, or USB hub, but can run the USB peripheral. But I don't know. I fumble in the dark. I'm just a biologist with a crazy idea. (crazy good!)

Some other researchers have mentioned and constructed foveated imagers. 1989 Van der Speigel et. al (UPENN), and Sandini et. al (an Italian group), around the same time. Misha Mahowald tried some "neuron-like" imagers, but I was never thoroughly impressed that this was the correct strategy. The human eye has a dens area of photoreceptors in the center of it, called the fovea. This was my idea, but other did it first. but, they never did it adequately. They never actually LOOKED at the human anatomy to see how many receptors were there.

I have been working on this idea since 2002, when I left undergrad school, and I incorporated in 2004 (Sams Antics Inc.), We (I mean ME) are a pathetic operation, but it is fun and exciting! The pixel sizes were coming down in the early 2000s, but they are probably at their minimum by now. Soon the optics will be the limiting factor on getting a clear image (and things like S/N ratio and fill factor and reflectivity of silicon and etc.)

Yeah, so, like I said, I was thinking of some DIMMs, with both SDRAM and Flash on it, as I hear that this style is "in vogue". Also, some RAID arrays come with slots for spinning platter mem and some for Hybrid DIMM SDRAM/FLash. Supposedly this aids in recovery speed (slow for chip mem) vs breakdown frequency (high for spinning platter; I think that is correct? I forget?). So, I have the SATA standards somewhere, but I think I should get a book that explains it.

I am in like the "technology book black hole" of America. Vermont like poetry and cookbooks and buddhist philosophy and cookboooks, but ask them a question about science or tech and its all "huh?". The yard sales are abysmal, and the bookstores assume I am a yuppie (rich) looking for a "coffee-table ornament". Its maddening and frustrating!

Yes, interleaving is the word! I forget (at the moment) about how many Petabytes, but humans don't have perfect memory, so neither will my strong AI Sam(uel) or Sam(antha) or just Sam (1% of the babies born on earth are gender ambiguous; maybe many more than that!). Sam will embark upon many antics, when I get him/her/it running.

The original sensor I had selected (first Nat. Semi, then sold to the now defunct Kodak-ISS (just before the bankruptcy; Kodak is now mostly a label; a shadow of its former self.), sold to a venture hedge fund firm in CA, flipped again and absorbed into ?ON Semiconductor? Or was it Omni? I forget?), will be one eyeball. I am hoping the next cheapest one (when I bought, the cheapest was 15$ per sensor, but some are online for 5$ now) has a similar output/interface. Anyhoo, the Kodak sensors had a eval board documentation, and it suggested an Altera FPGA (or was it PLD? PLA? or FPA? I forget these acronyms and I have never used one, so....mushy brains, I forget!).

I am looking just to stash the raw output for one day. At night, Sam will sleep (perchance, to dream?), and upload to a RAID array. Maybe USB to the RAID? I think this is standard, and not too slow. Human sleep is 8 hours, and with that much time, essentially, "optically idle", various processing and compression could easily occur.

So, if I get the flash mem set up--by interleaving, or maybe by using the latest USB 3.0 standards--I can just worry about stealing a few frames, here and there, to run the "now robot", the "thinking, acting being". As you can see, I am fuzzy on ALL the details!

This week I was looking at robot bones (carbon fiber rod) and their weights, and trying to get an idea of what sorts of motors I will want and need (probably stepper motors; but I need to buy a good introductory book on "All the types of DC and/or AC motors that are fit for robotics applications"; but I couldn't find a decent title on amazon or ebay, so, "the soi-che continues"). Also, slapped my second-rate Ohmmeter onto the carbon fiber rods and saw a nearly zero ohmage. I hadn't counted on that; but I guess it is better than something that would build a static charge. I will just be careful to insulate all my electronics and,?somehow? ground the bones to themselves, and the earth-ground.

Rob, it cost me alot to get some of the books I got on the subject of image sensors. I probably would have been better off to just read the pdfs of the image sensors, as intricate details of their construction was probably not necessary. however, long story short, I have a few of these books, and they are still expensive. I could slide you a few chapters here, and there, if you wanted. I don't get to chat with "colleagues" much so, just let me know and I'll spend an hour or two sharing what meager resources I have. Or, maybe I'll get that university job this year, and just buy you--and all my other friends--a copy for your birthday! (OK,I guess its safe to say, I will never be THAT rich).

I have Jim Janesicks "scientific Charge Coupled Devices", Howes? and Morgan? "Charge Coupled Devices", Nakamura "Digital Still Cameras and Sensors", And Theuwissen's book (I just have a photocopy of it) . I had Gerald Holst's work on the subject, but gave it to a friend who gave a me a good deal on an ancient (but not collectible.... I am just REALLY BROKE) oscilloscope. (I need one with a better bandwidth; 25 MHz is probably inadequate for just about everything non-audio (everything video).)

OK, let me know if you are interested in one of those titles and I'll put some files in a "put-locker" somewhere... (cloud is wonderful, huh?).

Jan Axelson's "USB Complete" (2001) has a list of old USB controller chips. She focuses on EnCoRE, Cypress CY7C637XX. Still available, so I will buy one. Passing references are made to EZ-USB but the part number is way different. Mine is CY7C68033, and she mentions AN2121 as being a Cypress EZ USB chip? Oh well. mildly confused.

Actually, she says there are three "categories" of chips for implementing USB. (1) Designed for USB from the ground up, (2) chips based upon popular families, and (3) designed for use with a microcontroller (i.e. the USB controller only handles USB signals and it needs an external microcontroller to control it) .

(1)EncoRE , mentioned above, and ScanLogic SL11R

(2) several options, most of it mentioning the 8051 microcontroller, and similar devices.

(3) USBN9603, USS820C, NET2888, PDIUSBD11

I looked up these, quickly, in arrow, and some were available and were back-ordered and some were "huh?".

I can't spend too much time down that rabbit hole. The tech is old, and things have moved on from there. But, I probably shouldn't ignore the 8051, since everybody seems to rave about it; a popular architecture, I take it?

Another good thing about the USB book I'm reading is, the hexadecimal code makes sense to me. EnCoRE uses just 37 assembly instructions. i think I can handl it. (bad news is, I think the EZ USB I was planning on using, might need to interface to an 8051; maybe EnCoRE is looking better by the minute! Luckily, these chips are about 3$!).

OK, I am in WAY OVER MY HEAD. If you try this, use google chrome as your browser and push the translate button. Otherwise, you'll be VERY lost, in the Cyrillic alphabet! (beautiful letters though; I shouldn't knock it!).

http://www.usbdev.ru/files/smi/

There are a few pinout diagrams, and such, on this page. Mostly for the 3257EN, LQFP package.