I've been kicking around the idea of building a 6502 computer for over a year now, and I started learning 6502 asm a couple of weeks ago.
I know what I want, but I wanted to check and make sure that it should work, before I start, as I am on a very tight budget.
I have a potential memory map,(this is the second revision) and I thought it would be best to ask the more experienced.

I got a whole bunch of 32K SRAM off of ebay for really cheap, and I want to make sure that my machine is not underpowered.
I want to bank my memory, I was considering stealing the last byte of the 8K SRAM and mapping it to some sort of mapping circuitry, using the lower nibble for RAM, and the upper nibble for ROM. That would give me 16 banks each for RAM and ROM. I was thinking of using a PIC, but I'm not sure if it will be fast enough. If not, I could probably just use a couple of latches and demultiplexers. For rs232 serial, all I have is a couple of 8250's a 68681 and a couple of 6402's. Which is better? Anyways, it's going to be a multi-board system with either a VFD or led display. The processors I have are an SY6502B and an R65C02P2 I'm not sure which to use.

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Peter: "Hey Mort, do these suppositories come in any other flavors?"
Mort: "Peter, your not eating those are you?"
Peter:(Sarcastic) "No, I'm shoving them up my butt, Of course I'm eating them!"

Why not use one of the ROM addresses, that way you don't need to lose any RAM or ROM bytes. Writing to the ROM address sets the page latch, reading from the ROM address reads the ROM. You may like to use two latches, one for ROM and one for RAM, this would then easily allow 256 pages for each block.

Also I'd steal part of the ROM space for the I/O, unless you need a whole load of I/O 1k or even 256 bytes will probably do.

Try to split the address range along as few high address lines as possible. This makes decoding easier, e.g. If you want a 32K block use $0000 to $7FFF or $8000 to $FFFF as you only need 1 address line, A15, to decode it.

Make the page areas the same size, then you can use the same code for address calculations in paged memory, makes life easier.

I would use something like this ..


* the banks are really 16K in size but 2K is wasted as the top 1K is never paged, so the vectors don't need to be replicated, and 1K is overlaid by the I/O area. Not a great loss as you would still be able to use over 3500K of the 4096K that having 256 pages would allow.

Lee.

I want to be able to read the latch as well, so I can easily figure out what page I'm on. That's why I was thinking of using the ram, I could have a buffer so it writes to both the ram and the latch, and reads the ram.

My first version had the first 32K of ram banked, but I realized that that might interfere with the stack. I plan to keep the ram for a possible sound card and video card, and the bootloader rom for any drives in the I/O area, as well. Besides, the mapping of the memory won't be set in stone, for the most part, there will be jumpers or dip switches on all of the cards to define the memory location.

I want to leave enough I/O space available for future use, so if I ever want, say, a video card, or something that hasn't been thought of or designed yet, as I don't and probably won't have enough money to build another one. I have built a couple on my relatively small breadboard and they worked.
Thanks for the tips.

_________________
Peter: "Hey Mort, do these suppositories come in any other flavors?"
Mort: "Peter, your not eating those are you?"
Peter:(Sarcastic) "No, I'm shoving them up my butt, Of course I'm eating them!"

Using individual bytes in the address map for one thing or another requires an awful lot of decoding circuitry, which means more parts, more work to wire up, and lower maximum clock speeds once you get it going. Do you have a particular plan for so much memory? Most first-timers use only a couple of K maximum; and then when they're ready to use more memory, they probably also have a better idea of what they want in a computer and they make another one. I think everyone probably starts out with the idea that their first home-made computer is going to be so grandiose and expandable that they'll never want to make another, but in reality it never happens that way.

If you can get away with 16K of RAM and 32K of ROM (or vice-versa), and 10 or fewer I/O ICs, you can do the entire address decoding with nothing but a 74HC00. That's it. You can see how my workbench computer does it at http://www.6502.org/users/garth/project ... chematic=2 . (Replace the inverter with another section of the 74xx00, and you can do it all with the one IC.) The main page for that computer is http://www.6502.org/users/garth/projects.php?project=1 although the pictures and some of the info is outdated now that I've added more to it.

If you really want all those pages of memory, it would be so much easier to use a 65816 which gives you 16MB of address space with the only extra hardware being a 74ACT573 octal latch. It may seem daunting at first; but when you move beyond rudimentary programming, the '816 really is easier to program, even if you don't need the extra memory capability.


>Anyways, it's going to be a multi-board system

Try to keep everything that needs the processor's own buses on the main board. Spreading it out really limits your maximum clock speed because of transmission-line effects and capacitive loading. If you really don't want to ever move beyond 1 or 2MHz, that's your business of course; but it will be hard to move much beyond that in a home-made multi-board system where the processor's own buses go out on the backplane to the other boards.


> with either a VFD or led display.

How about an inteligent character LCD? They're cheap, take almost no power compared to the VFD or LEDs, and are a lot easier softwarewise to feed than the LED display.


> The processors I have are an SY6502B and an R65C02P2 I'm not sure which to use.

If you have the 65C02, don't even bother with the 6502. The 65C02 doesn't just take less power, but has more bus-driving capability, more instructions and addressing modes, has the NMOS bugs and quirks fixed, you can stop the clock (as for debugging), the clock oscillator doesn't necessarily need to be separate, and the new ones have more interface signals and will work at much higher speeds.

I use a PIC for bankswitching in my project. It's not instant, some delays are needed on the 6502 side. I think you'd need a demultiplexer any way you do it though. I use a latch on the PIC too at $5xxx, it snags A0-A7 when the PIC's parallel port is written, so the PIC can use it for a jump table. I have other reasons for using the PIC though, for sound synthesis and it's UART.

BTW, did you say you want to put up to 16 32kB SRAMs on the board? If it helps, I'd be happy to trade my spare 512kB SRAMs for some 32kB ones I can use.

How do you use an 8250A with a 6502, as the only clock it has is for the baud generator?

_________________
Peter: "Hey Mort, do these suppositories come in any other flavors?"
Mort: "Peter, your not eating those are you?"
Peter:(Sarcastic) "No, I'm shoving them up my butt, Of course I'm eating them!"

"I've been kicking around the idea of building a 6502 computer for over a year now, and I started learning 6502 asm a couple of weeks ago.
I know what I want, but I wanted to check and make sure that it should work, before I start, as I am on a very tight budget."

If you are on a tight budget, get yourself an old Tan color Commodore 1541 Disk Drive. The control board is basically a SBC which contains a 6502CPU/2x6522VIAs/2K of SRAM/8K ROM @ $C000 and $E000. You can easily map more memory by adding/changing lines to the 74LS42 address decoder IC. You can swap your EPROMs for the DOS ROMs and get continuos ROM from $C000 to $FFFF. Most of the ICs are socketed. Put your reset pointer at $FFFC (low byte) and $FFFD (high byte) and your good to go. Plus you get +12VDC and +5VDC with the 1541, although the 5V line is all that is needed. The schematics for the 1541 can be found on the net.