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PostPosted: Mon Apr 04, 2016 1:44 pm 
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BDD,
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You are using a lot of bits to select I/O devices. As an example, in my POC unit, I/O starts at $00D000, which is the first device. The next device is $00D100, the next is $00D200, the next is $00D300, etc. This address progression is easily decoded using only three bits at the 74AC138 decoder's A, B and C inputs, plus a chip select that is true when A15-A12 is %1101 (a NAND gate driving /E1 on the '138 with A13 driving /E2 does it). The '138 A-B-C inputs are wired to A10-A8, which takes care of telling the '138 which device to enable when the I/O block is being addressed. Splitting up the I/O space into pages is efficient and demands minimal logic.

Generally speaking, as the "distance" between devices gets smaller and smaller, the logic required to decode the address space gets bulkier and bulkier. This is why most of the eight bit micros built around the 6502 (e.g., the Commodore 64) had paged I/O decoding.

If I am not mistaken, the memory map Garth had posted should require minimal logic as well.

(I don't have any idea how to convert a truth table to a boolean expression and I am not at my computer at the moment but here is a truth table)
Attachment:
Screenshot 2016-04-04 at 8.38.09 AM.png
Screenshot 2016-04-04 at 8.38.09 AM.png [ 5.57 KiB | Viewed 863 times ]


Selection of each IO should then be just a matter of using the correct address. The only issue with this approach is that it does allow for the addressing of multiple interface ICs at the same time (although as Garth has pointed out in his primer, this may prove useful in order to write the same data to multiple interface ICs at the same time).

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My recommendation would be to use the proper symbology. Once you get your unit running you may want to adapt a machine language monitor to it for debugging purposes. Just about every 6502 M/L monitor I have encountered uses the MOS Technology symbology for number radices. In other words, if you are going to live in France you need to learn to speak French. :D

I will try my best to do so, although I may slip up now and then :D.

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Last edited by billylegota on Mon Apr 04, 2016 6:13 pm, edited 1 time in total.

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PostPosted: Mon Apr 04, 2016 1:53 pm 
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Ed,
BigEd wrote:
Hi Billy - good to see some ideas being bounced around here. Bear in mind that you'll get almost as many opinions as respondents - to some extent you have to construct your own wisdom from what you see around you. For me, you can draw a memory map either way up. But zero is always described as low memory, and the vectors as at the top of memory. I think I tend to place them on the page accordingly.

As for hex, we see various conventions, and in almost all cases everyone will understand what you mean. 0xffff, $ffff, &ffff or just plain ffff. The thing to watch out for is that any given assembler (or other software) will have a strict convention. Many a time someone has written 10 when they mean $10, or vice versa, and the program is not going to behave the same way.

(We're all on first name terms here, unless someone has determinedly not used their first name, in which case their forum name or a derivative of it is fine.)

Cheers
Ed

For hex, octal, and bin I will use the conventions put forth by MOS and will use capitals (Garth is correct, f and 1 look quite alike on my, and likely others', display).

As for names, being raised in Texas the past 10 years I have been taught to use surnames with anyone my superior. From now on I will use first names / usernames unless asked to do otherwise.

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PostPosted: Mon Apr 04, 2016 4:43 pm 
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billylegota wrote:
(I don't have any idea how to convert a truth table to a boolean expression and I am not at my computer at the moment but here is a truth table)

Use whatever format makes sense to you. Here's how I did a "decoding table" for my POC V1 unit:

Attachment:
File comment: POC V1 Decoding Table
sbc_v1.6.0.gif
sbc_v1.6.0.gif [ 25.45 KiB | Viewed 854 times ]

I use a simple notation to express logic equations, in which & is logical AND, | is logical OR and ! is logical NOT. The table format makes it clear (to me, at any rate) what the address bus state must be for any given chip selection to occur.

Here is the corresponding schematic:

Attachment:
File comment: POC V1 Decoding Circuitry
decoding_ckt.gif
decoding_ckt.gif [ 39.43 KiB | Viewed 854 times ]

A goal I set during the design phase of the project was to have no more that two gate delays between the address bus and a chip select. With 74AC logic, the above circuit produces a worst-case prop delay of 24 nanoseconds from when an I/O device address is placed on the bus to when the corresponding chip select is asserted. I could have achieved even faster operation with 74ABT logic (shown in the schematic) but decided that 74AC was fast enough.

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PostPosted: Mon Apr 04, 2016 4:54 pm 
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billylegota wrote:
(I don't have any idea how to convert a truth table to a boolean expression and I am not at my computer at the moment but here is a truth table)


A Karnaugh map can be a useful assist. See here too, perhaps. But also, you can use programs like the FPGA vendors' tools to convert from one representation to another - HDL, schematics, equations, truth tables.


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PostPosted: Mon Apr 04, 2016 6:13 pm 
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Ed,

I took a look at tree reduction and Karnaugh maps but I can't really say that I understood any of what I read. Luckily I was able to find this program which does automatic equation generation from a truth table, minimizes the equation, and then *can* generate a set of logic gates that fulfill the equation (although it almost seems like cheating).

I used it above to generate my first diagram but I think that for my final I'll want to see if I can't come up with something myself based on the equation.

I am tempted to use BDD's approach as it seems more efficient with the address space, but the current map I have in mind will only need a single 74HC00 and I really want to minimize the number of ICs on (and therefore the size of) my board.

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Last edited by billylegota on Mon Apr 04, 2016 6:15 pm, edited 1 time in total.

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PostPosted: Mon Apr 04, 2016 6:15 pm 
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BDD,

Out of curiosity, what program did you use to draw that decode table? Are you just using your schematic editor?

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PostPosted: Mon Apr 04, 2016 7:41 pm 
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billylegota wrote:
BDD,

Out of curiosity, what program did you use to draw that decode table? Are you just using your schematic editor?

It's just a schematic editor (Express PCB). I prefer to work with simple tools, my theory being that complex tools consume too much of one's time with their often-steep learning curves, often demanding more than they give in return. I'd rather use my bench time being productive. :)

My approach extends to the actual hands-on aspect of building and troubleshooting circuits. Most of the time, all I use is a basic logic probe to troubleshoot, even though I have other test equipment at my disposal.

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PostPosted: Mon Apr 04, 2016 11:57 pm 
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BDD,

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It's just a schematic editor (Express PCB). I prefer to work with simple tools, my theory being that complex tools consume too much of one's time with their often-steep learning curves, often demanding more than they give in return. I'd rather use my bench time being productive. :)

My approach extends to the actual hands-on aspect of building and troubleshooting circuits. Most of the time, all I use is a basic logic probe to troubleshoot, even though I have other test equipment at my disposal.

Thanks for linking me!

I totally agree with your statement about complex tools. I have been trying to figure out Eagle for a few days now and it still seems unnatural to me (I have tried KiCAD and gEDA but those are even worse :?). I downloaded ExpressPCB and have found it much more intuitive (I especially like that the help page can be read in 15 minutes instead of 15 hours for Eagle) yet does not feel like it has been dumbed down (like Fritzing).

The only real downside that I can see is having to make custom components for all the WDC parts, but most other schematic / PCB packages suffer from the same issue.

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PostPosted: Tue Apr 05, 2016 6:26 am 
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billylegota wrote:
I downloaded ExpressPCB and have found it much more intuitive (I especially like that the help page can be read in 15 minutes instead of 15 hours for Eagle) yet does not feel like it has been dumbed down (like Fritzing).

The only real downside that I can see is having to make custom components for all the WDC parts, but most other schematic / PCB packages suffer from the same issue.

Be sure to visit EPCB's website, where they have a community library of different parts. Making your own schematic symbols isn't difficult. Attached is the EPCB component file for the W65C02S microprocessor to get you started.


Attachments:
File comment: EPCB Component: W65C02S (DIP40)
IC - WDC - 65C02 - Microprocessor (DIP40).s [2.82 KiB]
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