BDD,
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You are using a lot of bits to select I/O devices. As an example, in my POC unit, I/O starts at $00D000, which is the first device. The next device is $00D100, the next is $00D200, the next is $00D300, etc. This address progression is easily decoded using only three bits at the 74AC138 decoder's A, B and C inputs, plus a chip select that is true when A15-A12 is %1101 (a NAND gate driving /E1 on the '138 with A13 driving /E2 does it). The '138 A-B-C inputs are wired to A10-A8, which takes care of telling the '138 which device to enable when the I/O block is being addressed. Splitting up the I/O space into pages is efficient and demands minimal logic.
Generally speaking, as the "distance" between devices gets smaller and smaller, the logic required to decode the address space gets bulkier and bulkier. This is why most of the eight bit micros built around the 6502 (e.g., the Commodore 64) had paged I/O decoding.
If I am not mistaken, the memory map Garth had posted should require minimal logic as well.
(I don't have any idea how to convert a truth table to a boolean expression and I am not at my computer at the moment but here is a truth table)
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Selection of each IO should then be just a matter of using the correct address. The only issue with this approach is that it does allow for the addressing of multiple interface ICs at the same time (although as Garth has pointed out in his primer, this may prove useful in order to write the same data to multiple interface ICs at the same time).
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My recommendation would be to use the proper symbology. Once you get your unit running you may want to adapt a machine language monitor to it for debugging purposes. Just about every 6502 M/L monitor I have encountered uses the MOS Technology symbology for number radices. In other words, if you are going to live in France you need to learn to speak French.
I will try my best to do so, although I may slip up now and then
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