So, today I think I should post a small piece about my thoughts for "Memory Architecture for a Focal Surface Array Computer Utilizing the 6502-family Microprocessor". As is usually the case, I will be "hacking it", but this time, doing so with more "specifics" than usual.
My one or two month hiatus from these pages was an introspective recognition--an admission--of my "lack of depth" on this issue. Specifically, I needed to know (1) the types of memory available and their capacity, speeds/frequencies, fundamental unit cell, interface, purchase price, etc. (2) Bus switch characteristics, available products, prices, speeds, fundamental architecture, etc. (3) Timer-counter prices, availability, prices, speeds/frequencies/delays, and/or (4) necessity or non-necessity of DMA or other memory controllers, (5) interface to large storage and/or long term storage.
Driving all of these questions was my need to deal with large amounts of video data, quickly and efficiently (i.e. VGA, 12 bit (1.5 Byte) per pixel X 488 X 648 X 30 fps X 12 sensor array (6 per eye) X 60 sec/min X 60 min/hr X 16 waking hrs/day X 365.25 days/year X 75 years (robotic-humanoid average lifespan). In essence, 6 sensors at VGA is really only a 2 megapixel camera, X two eyes, is 4 megapixels. 30 frames per second is a decently "humanoid value" (i.e. according to Hugh Davson's "Physiology of the Eye", a reputable authority on the subject, the flicker fusion frequency, depending upon experimental assumptions and characteristics, hovers between 40 and 60 cycles per second). So, 269 Petabytes is the lifetime of raw video data for my robot. I have researched a few RAID arrays whose capacities approach that "regime", i.e. the "PB regime". Also I have perused a few brief descriptions of SATA (which, I will probably need, though perhaps thunderbolt might be a "new standard" to consider?). One extremely important point to consider, is that, for human-like intelligence, one does not need "perfect recall". In fact, such perfect recall would probably be detrimental to the proper functioning of a "Human-like Artificially Intelligent Robot".
Now, why 6502? Because I have a history with the processor, albeit, a cursory and somewhat emotional/nostalgic attachment. Secondly, it is accessible in a way that "new" technology, generally, is not. Thirdly, while it is a wholly inappropriate tool to use for the vision tasks that I expect to tackle, it might be an adequate (1) memory controller, i.e. for switching the bus between the various elements of the system, and (2) it might even be programmed to be the "voice chip" (a late realization I have come to, after tackling the "speakjet" magnevation chip, for a week or two!). I read a rumor, somewhere on the internet, that the speakjet is just a "pre-programmed PIC", but I think the author was confusing it with the BASIC Stamp? (If any of you out there in 6502-land know for sure, do let me know!). The Stamp is definitely a PIC, and though I bought the dang thing some ten or so years ago, I didn't find it a very interesting or insightful description of how a microprocessor works. I think, perhaps, it might teach BASIC language, but probably obscures more about microprocessors than it actually teaches. The book that came with it is useless, but one only learns this after one has downloaded the pdf manual with extensive documentation of how the BASIC Stamp really works (i.e. it works like a PIC!)!
Perhaps a multiprocessor 6502-system is what I should envision? OK, enough with the preliminary discussion. Let me launch into some concrete part numbers that I have been "mulling over". So for (1) counters, (2) Bus Switches, (3) FIFO/DPRAM, (4)?Intermediate storage?, (5) Permanent/Semi-permanent Storage, (6) RAID/MAID Permanent Storage, perhaps the following would serve admirably and/or suffice?
(1) Still researching (due to my concerns about propagation/gate delay/ripple/etc.). Have ordered a book on the subject from a college library, though I might be able to ferret one out on the internet (Some international scoff-laws think that scientific knowledge should be FREELY available! Imagine that! What a novel idea! Certainly not anything that people, like, have fought wars over, or anything silly like that! (sarcasm!)). I am settling on synchronous counters, obviously, but still don't know enough about counter construction and/or market availability to make a decision. One page that I went to recommended Xilinx products (interesting history to that company; a few executives spun off/out-of Zilog, itself a creation of Faggin!), but these appear to be PLDs and FPGAs and such. The original Kodak documentation (for my image sensors) indicated Altera, their (or "one of their") chief competitors in the FPGA/PLD market. I consider this overkill, for a mere "counter"; but I could be wrong. I lean towards synchronous counter, naturally, as asynchronous will "ripple" and have large delays, inadequate, I presume/assume to the proper completion of the task of timing transitions in a memory management/bus system.
(2) IDT QUICKSWITCH IDTQS32XVH384 (20 bit bus switch; no delay? can this be true? About a $1.50, or so.). Also of note, though less studied by me, was Crosspoint Buses/Crosspoint Switches. This, it should be noted, can be a confusing terminology since "crossbar" is also a term in computer science. I think it was TI that offered crosspoint switches on digikey? They were slightly more expensive, so I only ordered one, and have barely perused the documentation. (there is an article/blurb about the terminology confusion on this fine website!
http://thememoryguy.com/ . Also, note the recent promise/peril of the 1-transistor SRAM cell! While we heard rumors of this semiconductor species before, it never came to fruition. A new company thinks that they can do it! I guess we'll see!). (
http://thememoryguy.com/crossbar-or-crosspoint/ ).
(3)I am settling on AverLogic AL460A; or one of their similar offerings. This FIFO is the largest capacity I could find (at least, largest for under a hundred bucks). I suppose a 20 or 30 $ chip is nothing to sneeze at (especially if one has a tendency to break chips!). Texas instruments had a good/cheap FIFO (several hundred KB, 20 or 30 bucks?), and there was a Dual Port RAM from IDT (only 1 KB, but also only 10 bucks, approx.). There are options here, so I think I can be flexible, for now. AverLogic is a fabless-semi company, and they are advertising a new roll out ?soon? of a 32 MB FIFO, largest in the industry! I am just hoping to get my hands on a 16MB chip.
(4)? Intermediate Storage? Where should I shuttle all the information from the FIFO/DPRAM to? It needs to be large capacity, to deal with the inherent high bandwidth of the optical world i.e. video sensors. This would seem to limit us to two choices, SDRAM (DDR3 or DDR4) and/or Flash (EEPROM, NAND?) chips. I have ruled out SDRAM, provisionally, since I have little hope of interfacing to these devices, at my present level of knowledge. Though, perhaps, were I to purchase some DIMM sockets with SDRAM already on it, then I think I could tackle the SATA interface. So, that remains an option. (Note: on all discussions in this post, you should note that I have not worried about logic levels and/or power levels for the various technologies, assuming, that if there is some "sticking point" on this issue, that some solution can be easily implemented. Safe assumption? I dunno? Its a gamble.).
Would a FIFO or DPRAM be able to feed some SATA interface, and shove the data directly to a RAID array? Maybe. This seems appealing, but, I think, unlikely. Maybe there is some such thing as a "SATA controller" (IC?) that would do this? The data coming out of each image sensor chip is 33-to-45 MHz, 12 parallel bits (or "lines" or "traces"), and a pclk, hsync, and vsync trace. The latter three traces area available for driving counter circuits, and are programmable for rising or falling edge synchronization of the valid pixel data (i.e. synchronization with the memory chips that will receive said data). I see no problem getting the data into the FIFO and/or DPRAM, and back out of it again, but getting it into a larger capacity chip (on the order of GB) is priority, as no FIFO/DPRAM is that large, and the KBs and MBs "fill up quickly").
I looked at PSRAM (pseudo-static/Page RAM; actually a DRAM pretending to be an SRAM) briefly, but it is still in the low MBs regime, and GBs are what I am looking for. Of course, there is "data compression" and over time, even, "data discard", but the industry is certainly ready and able to do the things I envision. A 1 Petabyte (expandable to 4 PB, or so) RAID array exists, and can be bought for just a mere half million! (Other solutions offer a quarter PB, for far less, though populating the bare-rack array with the individual 6, or 8, or 10 TB SATA spinning platter HDDs is also an expensive proposition.). One should note that human biology is curious and applicable here; specifically some sort of implementation of the optic chiasm would be advisable. This, in addition to my original intention of a foveated image sensor (before I adopted the strategy of the "foveated, curved, focal surface array, Multichip module" concept) and in addition to implementations of binocular fusion and stereopsis, might--and probably would--result in further reduction of the size of the data. But this would require significant computation to achieve. This "intermediate storage" is probably a necessary step, since, any binocular fusion, and its attending data reduction, would best be implemented here, in "real time". (Note: I still consider the PSRAM, because, the interface is easy, just like SRAM; but unlike SRAM the densities are larger; i.e. low MBs regime.)
Some commentators--of an earlier age--have considered Strong AI to be out of the reach of computer scientists (Metamagical Themas? Douglas Hofstadter? I think? circa 1980s.), since it takes a mere 200 ms from the moment an image is introduced to a human subject to the moment when the person recognizes and identifies the image. In our present age, to a modern computer scientist, 200 ms might seem a lifetime. However, it does bear mentioning that sincere effort spent achieving this goal of quick image recognition is still a necessity, and it will not come easily or naturally. In short, much engineering will be necessary to achieve that goal.
And so, with the AverLogic chip I mentioned, reaching into the low MBs regime, the PSRAM seems less likely or necessary. And so, either a DRAM DIMM (Samsung has some in 128GB and possibly more), a 256 GB chip (Samsung made for mobile applications? Flash, I think?), a 512 GB (Flash?) SanDisk memory card, or some Flash EEPROM chips seem wisest, for intermediate memory. I know SDRAM (DDRs) are the "workhorse" of the industry (circa 1990s to now), but my "needs/wants" might be different from those of "the industry".
I am actually leaning, most, towards individual Flash chips, of 1 to 4 to 8 GB capacity (I think those were my options for capacity? And they seemed fairly cheap. Interface could be difficult; I shall read more about it. It might be possible to pick up a "kit" that advertises a FIFO to Flash/USB interface, and I will research that next.
(5) Once I learn SATA, it should be pretty straightforward to use spinning platter disks, or SSDs, or even Blue-Ray (MAID array? Massive Array of Idle Disks?) + cheap-ebay-purchased-Jukebox. The "memory guy" has a good article/graph about price per bit, over the past 2 decades. He still lists spinning platters as the standard and economical choice, though 2013-2014 had a slowdown in the decreasing price per bit trend. Also, I found a link, or two, to a Western Digital 10 TB, helium filled (to reduce friction, and thus, increase efficiency) HDD. I Think RAIDs are evolving too. With more platters the failure rate increases, and the redundancy might not be adequate to recover the information (i.e. if two disks fail simultaneously, it could spell trouble, as the data from the second disk must be used to reconstruct the data from the first.). I have seen some RAIDs with slots for SSDs and some for HDDs. Perhaps this is the best solution? SSDs, I gather, have reduced failure rates, and HDDs are cheaper per bit. So, the SSDs could back-up the HDDs.
(6) So, this item is not all that different from item (5), since both (5) and (6) will rely upon what I do in item (4) (i.e. still "indistinct"). So, why list a separate (6)? Because, I just wanted to comment and reiterate that RAID and/or MAID arrays are envisioned. The "mobile robot" should not have a "weighty" memory, as it must be "achin' and quaking and shakin', like humans do"--to paraphrase David Byrne of the Talking Heads. (As I write, I am in the public library, and some toddler, here, is presently giving her mother a "run for her money". Funny where "inspiration-to-write-and-design-and-engineer-and-create" comes from?). Downloads every night to the RAID/MAID structure are envisioned, and even a "dream state" might take place.
Now how about that? Do androids dream of electric sheep? I suppose I could write a specific program and introduce it periodically (like my own recurring dream of the ocean and waves and the sand running between my toes). But I digress. What companies make large RAID arrays? Well, even a small one of, say 32TB, might be useful to me. The empty rack can be bought for 65 to 100$, and populated with disks later. Buffalo (also maker of B-RAY drives), Synology, Rosewill, CineRaid, and GSpeedQ seem to be the small RAIDs that I have listed in my notes; they seem to be not-too-small and somewhat affordable. I think I have SansDigital listed as a supplier of medium sized, affordable RAIDs, though I see one or two offerings that I would call "Big" (i.e. 100TB or more). Finally, I found two suppliers of "Petabyte"--or fractionally so--regime arrays; PBRAID array (i.e. Nomadic PB) and Aberdeen (1/2 mill $, in 2012!). I also have listed a supplier of DIMMs (SDRAMs) called Dominator Platinum (Corsair), but I somewhat distrusted their flashy packaging. No matter; I have no "money to play with" anyway, so I will look beyond much of the packaging and find the "value" when I finally purchase something!
Those are my thoughts for today. One hopes that tomorrow will be more "reduced-to-practice" than today was! Cheers!
P.S. In summation, I might reduce the 6502 to mere "accessory controller", i.e. "memory manager", but I still like the idea of mere "phoneme/morpheme concatenation" being driven by this simple, elegant, fast, and historically YUGE (via Bernie, not Donald!) computer chip. As for video processing; that is another beast entirely! DSP! Yes! I'll cross that bridge when my knowledge, skills, and abilities allow it!
P.P.S. A serious question, to any who can answer. How many memory chips can be simultaneously driven by one image sensor? How many "Intermediate chips " (i.e. SDRAMs, Flash EEPROM NANDs, etc.) can simultaneously be driven by the output of a FIFO and/or DPRAM? It might be nice to have a bus that can branch to two memory devices and feed them simultaneously? Pipe dreams?