Getting closer ... Still some tricky routing on the lower left to be done, but I think I can see the finish line!I've managed to keep most critical clock signals on the top layer but the clock going to the 6510 port is still moving around a bit too much for my liking. I'll try to go after it at the next opportunity. I'm also going to replace the individual series resistors with 16 pin sockets to make things a little more manageable. Don't really have the room right now, so that will take some work. Probably will have to wait until next weekend ...

The ground plane remains intact (save for the vias, of course), but as mentioned, I am using the VCC plane to put some traces down - mostly just short bridges to get out of a jam. Hoping that's not going to hurt things too much. Here is what that looks like:That's it for now. Here's hoping next post will show a finished layout!

Cheers,
Drass

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C74-6502 Website: https://c74project.com

A milestone worth reporting ... 1st pass of the routing on the Registers Card complete

Well, almost ... I have yet to replace the series resistors with sockets. I created new packages for the through-hole ICs with octagon pads to give me a little more room. I think with some fancy footwork, I just might be able to get those sockets to fit. But it's not essential. The board is all wired up as it is so it's a good point to share. I'll sleep on the resistor sockets and may take another crack at it. In the meantime, here are some pics:

Top and Bottom:

VCC plane:

GND plane:
I'm very happy with how this turned out. The VCC place is a little cut up, but there are lots of bypass capacitors on the board so it should all work out well.

I'm going to take a hard look at it all and review it carefully but please let me know if anything obvious jumps out.

That's all for now. It will be on the ALU & CU Card next ...

Best,
Drass

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C74-6502 Website: https://c74project.com

It's not a big deal. The VCC doesn't really need a plane, as a bit of inductance between the power supply and the bypass cap only helps to filter the signal. As long as you have bypass caps close to the IC, and sufficiently wide traces leading to the cap (to avoid DC voltage drops), you should be okay.

The extra capacitance between the VCC and GND planes is too small to be useful, unless you a) work with really high frequencies (hundreds of megahertz), and b) take extra care (and pay extra money) to manufacture the board with minimal separation between the two layers.

Thanks Arlet. That helps.

On the topic of good bypassing, I ran across this article while following one of Garth's many helpful links: (http://www.sigcon.com/Pubs/news/9_07.htm). It deals specifically with connections to bypass caps when using planes and suggests independent vias from the planes to Bypass caps in that case (rather than for example a wide trace connecting VCC through the positive end of a bypass cap I.e., VCC via -> cap +ve node -> IC VCC pin).

I've ended up using various schemes on this board. I placed one bypass cap close every IC VCC pin and sometimes had the space for independent vias. Most often, however, I used the second method above which saves a via, and even occasionally had to resort to two capacitors sharing vias from the planes. At other times, it was convenient to place the via between the IC's VCC pin and the bypass cap, effectively sharing the via with both rather than VCC going "through" the cap to the pin.

I understand these more restricted paths will likely reduce the effectiveness of the bypass caps but your comments above seem reassuring in that regard. That said, I am contemplating using 74AC chips with fast rise times, so I want to do my best to avoid problems from the start. I'm wondering now whether to go back and work to eliminate those "shared vias" just to be safe. Does a via shared between two caps still provide a sufficiently low impedance path? Does placing a via between pin and cap render the cap ineffective? I would appreciate some perspective as I could easily be over-thinking things. After all, this is far from a "high-speed" board by modern standards.

Thanks in advance for any thoughts and suggestions.

Regards,
Drass.

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C74-6502 Website: https://c74project.com

These scary articles are usually geared towards people who design with 0402 or smaller surface mount parts, BGA packages, and a few hundred MHz signals. At the speeds you're working with, you'll get away with a lot worse. The SOIC packages and 4 layer board are already very helpful in reducing inductance. For a corner pin on a big DIP package, the inductance inside the package (that you can't do anything about) is equal to a few dozen vias. Even if you have to add one or two vias, the SOIC packages are still 10 times better.

Just the dose of perspective I needed. Thanks!

I'll keep moving forward and try to make a start on the second board. Very exciting to be making progress.

Cheers.

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C74-6502 Website: https://c74project.com

I guess it's a rite of passage ... No sooner had I declared the pcb routing "complete" than a problem showed up. Turns out that the 6510 AEC line puts not only the address and data buses in a high-impedance state, but also the R/W pin. The data sheet I was using was ambiguous in that regard and I had made the wrong assumption. The 65C02 has this behaviour as well for the BE signal, so there was no fighting it. I needed to put a tristate buffer on the R/W line.

As it happens, the 6510 port had left some unused single bit buffers on the board since it does not expose bit 6 or bit 7. So, after commandeering one of the available 74126 buffers, it was relatively straight forward to make the connections for the R/W signal going to the pinout headers. It was only then that I realized just how tricky dealing with the pcb was going to be. First, Eagle had left the old traces intact (those connecting the buffer I was using to the 6510 port elements from before). Deleting a connection in the schematic removed only the final segment on the trace, not the whole thing. So, now I had fo find and carefully clean up the redundant traces before routing the new connections. It's a crowded board, so it took quite some effort to find reasonable paths for the new airwires. All in all, what would have been a quick change with only a schematic to worry about, had turned into quite an operation now that a fully routed board was also in the mix.

Then I got a note from Dieter (thanks Dieter!) who had noticed that the AEC input signal was not going through an HCT variant chip to properly deal with TTL levels coming from a C64. More changes ... And then, would you believe it, I found a VCC pin I had managed to surround with traces on the VCC plane and was therefore completely isolated! I've now deleted the polygons and run specific traces for all VCC and GND connections just to be sure I haven't missed others. And so it goes ...

Sounds silly but I'm only now beginning to fully appreciate the implications of making the pcbs. I mean, a tiny mistake can render the whole thing useless. Given the cost of manufacture, it pays to be very sure before sending the order to the board house. Frankly, it's another one of those things that makes me think I perhaps should have started with a simpler project

Anyway, hats off to anyone who has managed the get working pcbs first time! Somehow I get the feeling I won't be joining those ranks anytime soon.

Cheers,
Drass

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C74-6502 Website: https://c74project.com

The best part of making a PCB is when you stare at the layout screen for hours, and everything seems okay, and the instant that you get the manufactured boards in your hands, you spot a mistake

Boards with internal layers are even more frightening in this regard. If you are lucky you find a missing connection, say a pin not tied to Vcc. Worse is a connection where there shouldn't be one. No way to fix that. I guess SMT might make that kind of mistake fixable with fine trace cuts to the via, but if it's right next to a pad...

Check, check and check some more! Good luck!

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8 bit fun and games: https://www.aslak.net/

I've fixed it, by looking at the CAD to determine where I have to drill holes (one on each side of the short to isolate it) that will sever only the one trace and not something else, then making the connection by soldering wire. However, that was from a manufacturing defect (not a design defect), where there was an etching problem because of contamination keeping the etchant from removing all the copper it should (yes, at a commercial board house!), and the trace was shorted to something else as a result. If it's shorted at a hole with a part's pin in it, the pin has to be lifted from the board and connected by wire to the proper place. Not fun.


Here's a pretty foolproof checking method I use: viewtopic.php?p=17653#p17653 I've done very complex boards (up to 500 parts) with it and not gotten any errors in the final result.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It was this "nightmare scenario" that I was referring to. SMT mitigates this a little, if you have sufficient distance between the pads and the vias where you can insert a scalpel.



It was, mostly, schematic checking I was referring too. I know you hate them Garth, but the DRCs are of some use. I think if you want 100% out of every square mil/mm of the board you might need to go the extra mile with manual checking but if you are content with 99% the computer does a pretty good job, for free. Of course this depends on the tools.



FWIW KiCAD does not have that problem. Several times with my recent board, my first with KiCAD, I modifed the schematic. Upon applying the new netlist to the PCB you have options wether to remove removed components or traces. The whole trace will be gone if that's what you want. Not that KiCAD is anywhere near perfect, mind.

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8 bit fun and games: https://www.aslak.net/

If anyone is using Express PCB's software for design they can also use a tool developed by Marty Flickinger that examines a PCB and its matching schematic in detail to ferret out errors. xCheck is free in the sense that it is fully functional as downloaded, but has a nag screen asking you to make a modest donation. Once you do so and enter an "activation" key the nag screen goes away.

I've used xCheck on a couple of my designs and it pointed out some things that could potentially result in a problem with a manufactured board. It's all dependent on you drawing an accurate schematic and linking it to the PCB. Once this is done, even the most trivial error will be caught, along with DRC violations and outright layout mistakes, such as traces intersecting each other even though they aren't supposed to connect, or pads and via that are too close to each other or to traces. I've placed all sorts of intentional errors into some of my boards to see if xCheck would pick up on them, and it did every time.

Another tool, Copper Connection, can convert EPCB board layouts to Gerbers, breaking the vendor lock-in that EPCB has over PCBs designed with their software. Copper Connection is a full-featured board layout program, but I got it mainly to convert my EPCB designs to Gerbers. A license must be purchased to be able to enable the EPCB-to-Gerber conversion feature.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks for the comments gents. I think Eagle CAD has a good set of checking tools as well, including highlighting unconnected traces, overlaps, design rule issues, etc. The schematic checks are useful also in finding those times when a net looks to be connected to a pin but is not, for example. But I agree there is no substitute for desk-checking. You can be sure I will do my best to "check, check and check some more", as aslak3 puts it.

Realistically, given my lack of experience, serious problems are likely to be the result of faulty logic, incorrect timing or misinterpreted specifications. Logisim has been invaluable with the first category, but I'm afraid the remaining two have no equivalent safety net. I suspect there's no avoiding a bit of a white knuckle ride in this respect.

Certainly it's comforting to learn about various methods to rescue faulty pcbs post-facto, but also a little disquieting that evidently these are not in infrequent use even by experienced engineers. And I must admit to a brief smile at the discovery that a scalpel is a preferred tool for pcb "surgery". But drilling to correct an inner layer trace, now that seems like pure genius to me, amazing!

It's been quite a journey already, and the remainder promises to be no less so. Many thanks for everyone's support and interest along the way.

Best,
Drass.

P.S. Aslak3. I really liked the "push routing" in KiCAD that your website pointed to. I'm pretty wrapped into Eagle right now, but that feature alone makes a switch worth considering.

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C74-6502 Website: https://c74project.com

With surface mount parts the simplest thing is often to just bend a pin up and put an insulator under it, and then add a bodge wire. Part of the art of laying out PCBs is anticipating where the screw ups are likely to be and allowing for potential bodges in advance

I decided to take a pause from routing and look at 65C02 compatibility. Realistically, this is the last opportunity to add any significant changes to the hardware before working on the ALU&CU card, so it's a good time to make final decisions. My primary target is the Commodore 64, which of course uses the NMOS chip. Nevertheless, it would be nice to have this CPU be able to live alongside newer designs which use the 65C02.

It turns out that the majority of 65C02 instructions can be implemented with only microcode changes on the existing hardware (BRA INC/DEC A, zp addressing mode, etc). Similarly, I already have hardware in place to correctly add an extra cycle in decimal mode to produce valid flags. TRB and TSB can also be managed largely in microcode, but do require the ability to set only the Z flag after an ALU operation. Currently Z is always set alongside N so this needs to change. I'm out of room on the SF.MX decoder that controls the flags so some re-working will be necessary. But this seems fairly manageable. (For example, SEI and CLD can be combined and we can then use the "65C02 mode" jumper to control whether a CLD is performed during interrupt service routines. Other optimizations are possible as well).

RMB and SMB require the addition of a decoder (74138) to map bits 4, 5 and 6 of the Opcode to the correct bit in an 8 bit mask. We can then use the ALU to invert the mask as necessary to set or reset bits (with OR and AND operations respectively). BBR and BBS require a 74151 controlled by bits 4, 5 and 6 of the opcode to select the right bit in the operand for the branch test. Once again, the ALU can be used to invert the operand as necessary for Set vs Reset. The output of the 74151 can then be combined with the existing branch test logic for the other flags and fed directly into the sequencer at that point.

And I think that's it for hardware mods. All in all, it seems well worth the effort. Of course, I was hoping any changes could be done on the as-yet-to-be routed ALU & CU card alone but a few (small) changes to the Registers card are required (mainly the 74138 bit mask generator needs to go there). Once again, I'm faced with some re-routing on that board. but I will just have to grin and bear it.

One question is whether to implement STP, WAI or the VPB and MLB pins. I have also left the SO pin un-implemented for that matter. My assumption is that these functions are seldom used and can therefore be safely left out. I may be way off base on that though, so I would appreciate any feedback on that score.

Thanks in advance for any thoughts or comments.

Regards,
Drass.

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C74-6502 Website: https://c74project.com