non volatile RAM disk, looking for the cheapest storage chip

[legacy]

6502.org wrote:

Image no longer available: https://www.imageupload.co.uk/images/2016/01/29/idp-ram-disk.png

I am trying to add a storage device to my board, I'd like to have something as big as possible
my board has 5 slots, each slot is capable to address up to 16 Mbyte over a 32bit parallel bus

currently in use chips DS1265Y
chips, whose datasheet claims:

• fully static nonvolatile SRAMs organized as 1,048,576 words by 8 bits (1Mbyte)
• 5 years minimum data retention in the absence of external power
• Data is automatically protected during power loss
• Unlimited write cycles

the above PCB draft shows the initial idea where I planned to use four NVRAM, in the theory I have enough space on the each DIP socket to address 4 Mbyte per chip, but I can't practically find anything greater than 1Mbyte (I mean at cheap price, a NVRAM chip of 2Mbyte (1) costs too much), so the ram disk is going to be (1x4=) 4Mbyte of total storage size, just because I found 4 chips shipped for 50 euro (second hand, and they work fine).

OK, so here we are with the topic questions: what do you suggest, guys ? FeRam ?
Do you know a cheap FeRam chip, which comes with 3.3V/5V, 8bit data interface, 2..4Mbyte per chip ?
All of this, at cheap price ? (say, "it's cheap", if it costs a quarter than Dallas price for their NVRAM)

thanks


(1) e.g. DS1270Y, 2Mbyte

[GARTHWILSON]

The 4-megabyte 5V 10ns module I offer is much, much cheaper, smaller, and faster, and can be battery-backed as shown in this post as an example. Pictures are on the front page of my website (linked below), and the data sheet is at http://wilsonminesco.com/WM-1_4Mx8SRAMmodule1-2-17.pdf. [Edit: Darn. Cypress changed the CY7C1049 SRAM I use in the modules so it's no longer battery-backable on flea power. I changed the WM-1 module data sheet URL to point to the newer one.]

[legacy]

GARTHWILSON wrote:

The 4-megabyte 10ns module I offer is much, much cheaper and smaller, and can be battery-backed

oh, good, and interesting, with two of those modules I will be completed

[GARTHWILSON]

I edited (added a little to) my post above.

Another possibility is that if it's for file storage, you could use a serial flash memory, like the 25FL164 in an SO-8 package.

Disadvantages:

• You can't use it like normal RAM (use it like a disc instead).
• You'll have to write software to interface to it.
• You'll have to use voltage translators if your board only has 5V. (The flash is 3V.)
• You'll need to use an SO-to-DIP adapter if you want to plug it into a DIP socket.

Advantages:

• It is extremely small by comparison.
• It is very cheap by comparison, even after buying the SO-to-DIP adapter.
• It requires no battery backup to prevent loss of content.

[legacy]

ummm, I'd rather avoid the flash technology if it's possible, I do not like it at all

I can put a CPLD in the middle
in order to translate an asynchronous data access into synchronous SPI serial access
with a FIFO under the hood, of course

p.s.
no problems with voltage level shifters

[GARTHWILSON]

The serial flash is definitely not random-access, and you can't access a byte in one 6502 cycle no matter what you do in a CPLD. It's for use more like a disc drive. I've used it, but you have to give it instructions, then an address (and that right there takes lots of SPI clock cycles), then from there you can read bytes sequentially.

[legacy]

GARTHWILSON wrote:

The serial flash is definitely not random-access

a flash chip is randomly-accessable ONLY in read mode, there is no problem about that
troubles come when you have to write because you have to erase things "per page" before you can write on it
this makes flash writable per page-oriented instead than byte-oriented
(plus the special algorithm you have to follow in order to UNLOCK the page in order to complete the writing)
and this is the reason of the buffer and FSM I was talking about

in the theory the wicked trick "could" work
under the strict hypothesis that the buffer has enough space to accommodate two flash pages, at least,
there is no bust data coming from the bus, and the bus is not randomly accessing things out of these pages


however, I am definitely NOT interested in flash

[legacy]

about the above idea: FeRam-Serial

about parallel NvRam, CY14B108L seems interesting

[GARTHWILSON]

legacy wrote:

GARTHWILSON wrote:

The serial flash is definitely not random-access

a flash chip is randomly-accessable ONLY in read mode

The qualifier was the word "serial." Here's the timing diagram to read from the 25VF032 4Mx8 serial (SPI) flash in an SO-8 package:

After you select the part, it takes 48 SPI clock cycles (or 40 in the non-high-speed mode, good for up to 25MHz clock) before you have the first byte of the read.

It is possible to write one byte at a time, but the byte must be erased, and you have to give it a write-enable instruction before writing. After giving it the byte-program instruction, it takes 10µs to complete it. It writes the whole page, even if you've only specified one byte. The rest of the page just gets the same data it already had. Here's the diagram for the byte-write instruction:

Minimum write endurance to a sector is 10,000 cycles. SRAM's endurance of course is infinite.

Quote:

however, I am definitely NOT interested in flash

It is a pain, but the tiny size of the serial part makes it nice for something like file storage, and it's less work to connect with so few pins.

I have not looked into FeRAM. I am interested. Note however that what you linked to is serial also, like the serial flash above. Someone is developing a one-megabyte FeRAM module for my HP-71 hand-held computer. At the moment, mine only has 176KB which is all my budget allowed when I got it in the late 1980's. The CY14B108L NvRam is about ten times the price of SRAM.

[legacy]

GARTHWILSON wrote:

It is possible to write one byte at a time, but the byte must be erased

Parallel flash chips (e.g. Spansion) usually need to erase the whole page and you can't erase just a byte, I am not sure about the byte-erase, btw, supposing you can't, I was thinking about a sort of write-back mechanism: you write into RAM (the buffer I was talking about), then, once dirty, the whole page is written into flash (and of course, in this working scheme, before writing, you need to erase the page)

Within the buffer size it works like a write-back cache, it's not exactly "randomly" access, but, within the allocated pages, it provides a few more degrees of freedom than flash

GARTHWILSON wrote:

it takes 10µs to complete it

this will be handled by a specific FSM (FPGA side, probably a CPLD is not enough due to the high complexity of the flash programming), my board already comes with DTACK in its bus, so I can handle the bus into "busy" until the mechanism has completed. No doubt it's a bit complex, and requires strict constraints, but in the theory it could work

As written I am not interested in flash, however I believe the idea (of serializing things, from the parallel bus, to the SPI bus) will work for SPI-FeRam, which comes with no page/byte-erase, and that removes the strict constraint, even if it's up to 40-50 clock time slower than the parallel method and requires the BUSY-DTACK-handling that I was tailing above. The good news is that I can find SPI FeRam for cheap, and they come in big size.

is it acceptable? I say it's a compromise

PROs

• cheap
• big size

CONs

• complex
• slow

Concerting the CY14B108L chip, it's 2Mbyte parallel/8bit/3.3V, and it costs 38 USD per chip (qty<10). I would say "interesting"

p.s.
I am a bit shocked about prices
littlediode_components (ebay co uk) sells DS1270Y-70 (2Mbyte parallel/8bit/5V), at GBP 35,89, Circa 47,05 euro (brand new)
while Mouser sells at 278,50 euro

[Alamorobotics]

Howdy...

Very interesting thread, I'm looking into adding memory to my W65C816SXB board, this seem like a perfect match...