One of the glaring omissions in the Express PCB (EPCB) schematic and board CAD software is a means to weed out errors that may go unnoticed until after the new boards have arrived. As it so happens, Marty Flickinger of Xetec Inc. fame (the CBM peripherals maker) has released an easy-to-use program called Xcheck to address this omission.

Xcheck examines a schematic and the PCB design to which it is linked in an effort to uncover many common and not-so-common design errors that can result in a malfunctioning or DOA project. You get a complete report, including number of holes, traces, planes, etc., and a detailed list of all detected errors. I have given this software a pretty good workout over the last several days and can vouch for its effectiveness.

Xcheck is freeware but a "nag" screen will ask for a donation—the "nag" screen will go away if you donate at least 20 USD. You can download it here.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The problem is why I describe the pretty much foolproof checking method a boss introduced me to 25 years ago, at viewtopic.php?p=17653#p17653 .

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Express PCB software needs the option to tent vias, in their software, in order to support BGA IC's.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I decided to pay the Xcheck verification tool "donation" (obviously not really a donation if a certain amount of metaphorical arm-twisting is involved ) for this software, since the tool has proved to be useful. Any donation of 20 USD or more will get you a code to register the software and get rid of the nagging. You also will get free E-mail tech support and access to new features as they become available. Considering the amount of money that could be wasted by having defective boards produced, 20 bucks is very reasonable, in my opinion.

Anyhow, I've been using the software to verify some (non-computer) module designs and would like to share what I've learned so far.

1. Xcheck reads the schematic and PCB files directly from the disk. All this means to you is that you must be sure to save the most recent copy of these files before running Xcheck on them. If you forget this little step you'll be tearing out hair trying to understand why the errors that you supposedly fixed keep on being reported.
   
   
2. As more editing is likely to be done to the board layout than to the schematic, I suggest that you get all warnings and/or errors in the schematic put to bed before tackling the PCB. Be sure to use the Check schematic for netlist errors function in the EPCB schematic editor before checking the schematic with Xcheck.
   
   Note that "warnings and errors" refers to structural problems with your drawing, not the circuit design itself. Only you can spot and correct circuit design errors. If you connect R1 to C2 when you meant to connect R1 to C3, Xcheck won't know the difference and will not report anything wrong, unless your error accidentally ties together two distinctly different nets, e.g., Vcc and DB7.
   
   
3. Checking the schematic will either give you a no errors or warnings result, or a list of things that Xcheck thinks are wrong with your schematic. As I was playing around with the software I intentionally inserted a variety of structural errors into the schematic. No matter how obscure the error, Xcheck found and reported it.
   
   As Xcheck is computer software and not a human brain, it may report some errors that initially won't make sense. For example, if a connection from R1 pin 1 to R2 pin 2 is accidentally connected to R3 pin 1 as well, and R3 pin 1 is (correctly) connected to C1 pin 2, resulting in two different nets being attached to each other, you'll get multiple error reports, one about the real error (the accidental connection to R3 pin 1), along with secondary errors reporting that R1 and R2 are also connected to C1. Conceptually this is correct—if you were to wire the circuit as drawn, that's what you'd have. In this sort of case, the only connection of interest is the erroneous one between the R1-R2 connection and R3. So don't panic if a whole slew of errors are listed. In most cases, there will be only one real error to track down and fix. Start at the top of the list, fix the obvious ones and run the checks again. Naturally, don't forget to save your changes before rerunning Xcheck.
   
   Along with the errors and warnings report, Xcheck will also display netlist statistics and can even generate a bill of materials, whose value will depending on how well individual components are described in the schematic. I personally don't find the BoM feature to be useful, as all of my schematics include a detailed parts list.
   
   
4. As with checking the schematic, checking the PCB will generate errors and warnings, depending on what is found. Essentially there are two types of errors that will be reported: design rule check (DRC) and verification (physical layout) warnings and errors. Warnings are just that: Xcheck is not comfortable with whatever is being flagged. Errors, on the other hand, should be fixed, as failure to do so could result in a board that will not work as expected.
   
   As the design rules for EPCB-made boards vary according to the service being purchased when the boards are manufactured, it is necessary to tell Xcheck which service you are going to use. The Edit button on Xcheck's menu bar will drop down a little submenu, from which you would select DRC Rules. In DRC Rules, you select the service that matches what you plan to use. The selected rules are then the criteria for determining what constitutes a DRC error.
   
   It's important to select the correct service, as selecting a wrong service for the PCB design in question may produce a blizzard of errors when Xcheck is run. Also note that it is possible to edit the design rules, which feature could be used to qualify a PCB layout that will be manufactured by someone other than EPCB (tools exist to convert the EPCB proprietary design file to industry-standard Gerber and Exelon formats). Editing the design rules for the available EPCB services is a no-no, as doing so makes it theoretically possible to "qualify" a PCB that cannot be manufactured by EPCB.
   
   DRC errors will arise for such contretemps as adjacent traces too close to each other, use of a via, pad or trace size not supported by the EPCB service you plan to use, objects too close to the board edges, etc. I intentionally put a variety of DRC type errors into the PCB layout for POC V2 and Xcheck found everyone of them. The offender's coordinates are listed in the DRC report, making it a relatively painless process to track down the location of the error. As with schematic errors, start at the top of the list, fix the things that you can readily identify and then rerun the checks. Oftentimes, fixing one or two errors will clear many errors, for the same reasons as described above in the schematic check.
   
   
5. Along with the DRC report, a separate verification report will list such things as missing or misrouted connections, accidental contact between traces that aren't part of the same net, unconnected pins, etc., in short, anything that doesn't agree with the schematic. As with the DRC report, the verification report will generate coordinates to assist you in tracking down the problem(s). Here again, work from the top to clear errors.
   
   An interesting problem arises in designs in which not all pins of a part are to be connected. For example, pin 12 of the PLCC-44 version of the 65C816 is a "no connect," which means it must not be connected to anything at all. When I first ran Xcheck against my PCB it kept complaining that nothing was connected to pin 12, which constituted a verification error. A little reading and I learned that a special net called no_connect__ is recognized by Xcheck as meaning "no connection." So I created a symbol named no_connect__ and attached it to every pin of every part that was to be a "no connect." End of problem!
   
   The caution is that when using the Highlight net connections in the EPCB PCB editor as you route traces, all the pins that are attached to the no_connect__ "no connect" symbol will be highlighted. Needless to say, that could fool you into thinking those pins should be wired together (Ouch!). What I do to avoid this confusion is put an X on the silkscreen layer on each such pin so I know that it is a "no connect."
   
   
6. Not surprisingly, Xcheck's run time while checking the schematic or PCB varies greatly according to complexity. It appears that the number of nets has a significant effect on the run time, as do the number of traces and connection points on the PCB. A four-layer design potentially increases that run time, as any pads or via that are to be attached to an inner layer have to be checked for the presence or absence of such a connection.
   
   For example, a small module I designed that has only a few nets, a small handful of parts and is on a two-layer board completes the PCB check in about three seconds. In contrast, a verification of POC V2's PCB, which has four layers, 100 components, 704 connection points and 1424 separate traces (the trace count is corner-to-corner, endpoint-to-endpoint or endpoint-to-corner), takes about 40 seconds, running on Windows XP SP3 on 2 GHz AMD Athlon 64 hardware. I also tested on a Windows 7 box running the same hardware and it took 43 seconds (suggesting that the 64 bit Windows 7 is bit of a dog compared to the 32 bit Windows XP).

The above pretty much covers it. If you are using EPCB for your design work I recommend you get and use Xcheck. It could save you a bunch of grief, especially if you are still learning how to do good schematic and PCB layout.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!