Rob Finch wrote:
I've been experimenting with error correction recently, and I was wondering how difficult it would be to adapt the core to 10 bit bytes ?
(10 bits + 5 bits for error correction fits well into 16 bit word).
Interesting. I've been thinking/planning along the same lines. There should be no restrictions to including error detection and correction logic with the core's functions. Although the core is designed for 8/16 bit operations, the memory interface is implemented using the standard 8-bit byte. Extending that interface to 10 or more bits should not be an issue.
Rob Finch wrote:
How hard would it be to use another bus interface (eg. WISHBONE) ? WISHBONE requires ack pulses rather than a ready signal which kills the single cycle nature of the 6502 bus. But WISHBONE is freely available and there are a number of cores that use. it.
There's no reason that WISHBONE couldn't be used. As you say, the ACK responses destroy the single cycle nature of the 6502 memory cycle, but WISHBONE offers some improvements to the 6502 memory cycle that can be used to advantage. The ACK response can be mapped to an internal ready signal, and that should enable an easy port to the WISHBONE bus.
Rob Finch wrote:
Do you have a tool to convert text to micro-code instructions ?
I have a simple (Windows) tool available on
GitHUB that can be used for converting microcode text files into Xilinx memory initialization files. Alternatively, it can also produce VHDL compatible ROM structures that you can drop into your code. (It can produce Verilog compatible ROM structures, but I've never focused on that because my teams use VHDL. I use/prefer Verilog and I definitely prefer to use the Verilog memory initialization methodology. Thus, the Verilog output file can be used in most designs with a few edits, most of which can be automated with editor macros.)
I am still, unfortunately, working on the M65C02A core. It's not presently on GitHUB. A prior, incomplete release, which may be suitable for your initial foray into microprogramming can be found on
GitHUB. It will differ in a few minor areas, but it will fully implement the W65C02S instruction set, and it has most of the M65C02A prefix instructions implemented. Not present are the single/block MOV instruction, the accumulator/memory exchange instruction, the FORTH VM, the IP relative with auto-increment instructions, the Kernel/User modes, and the co-processor interface.