I have some comments.
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The AVR instruction set seems to have been influenced in part by the 6502. Many instruction mnenomics are similar, or even identical.
Surprise, all processors work with an ALU and have opcodes for arithmetic and logic operations supported by that ALU. They all need to control program flow. So they have conditional branches, jumps, subroutine calls and returns. I can't see anything 6502 specific in the AVR instruction set but agree, that they have common roots with all central processing units ever designed.
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1. Half the branch length as 6502 (-64 to +63).
The flash ROM is addressed as 16-bit words. So the actual branch range in bytes is the same.
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2. No real indexing modes, must use an indirect register. However after initialization, these can auto-increment or auto-decrement.
Only load and store is supported, no ALU ops. IO registers have their own IN, OUT, SBI, CBI, SBIS & SBIC instructions, but are also mapped together with GPRs and RAM and can be reached by load and store to and from the RAM address space..
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3. Modified Harvard architecture, separate instructions are required to read from RAM and ROM.
More important: You cannot execute instructions from RAM!
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4. A more complete instruction set (but also more to remember).
Again, they have an ALU with similar capabilities. However, Atmel chose to supply redundant mnemonics for the same machine operation. For example: ORI is also SBR (set bits in register), CLR is an EOR self, status bits can be set and branched on by bit # or function...
Immediate ops have their own mnemonic instead of an operand modifier (#). They occupy most of the 16-bit instructions: immediate operand = 8 bits, 16 registers addressable = 4 bits and of the remaining 4 bits for the ALU operation 5 of the 16 codes (ANDI/CBR, CPI, LDI, ORI/SBR, SUBI) are used. No room is left for EORI or ADDI.
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5. No zero-page, but 32 registers which can be used in a similar fashion.
They are true accumulators and support all ALU operations. Most ops accu to accu and immediate to accu take only 1 cycle!