Have been absent from this (my major thread) for some time, due to "lack of a concrete plan". well, not entirely accurate; lack of a concrete "digital design" plan. The "scientific hypothesis" is still a novel one, and one that is in need of "reduction to practice". So, there is much "planning" behind it (and in front of it!).
https://en.wikipedia.org/wiki/Leaky_bucket ; immediately conjures up memories of Ricky Nelson's "My bucket's got a hole in it (it don't work no more")"! Ha! No, I 'm not old enough to have a valid excuse for knowing about that song, nevermind having it on "instant recall", in my brain!
Today, I'm looking at "the market" (mostly digi-key) to see what is available for dual port SRAM. (This is probably VERY late to be asking this question, but does the 6502/65xx/65816 etc. system REQUIRE Asynchronous RAM? Or is it just easier for beginners to understand? I probably won't gain much using Synchronous RAM, except the hassle of "bringing the clock with me" everywhere I go? Mightn't some DRAM serve my project well? Hassle of the multiplex, and refresh circuit, though? I find the video signals I want, and have designed, are very high data-load. I am not ENTIRELY un-knowledgeable about DSPs and the "1990s" IC advancement; but certainly I am unexperienced; high clock speeds and SMT devices discourage my gaining such experience.)
It is possible for me to investigate the FLEX Altera FPGA (PLD?) that the kodak/nat.sem. image sensors originally had placed on their development boards; but PLA, PAL, and FPGA might be more flexibility than I want or need. Regular old fashioned hardware design will be just fine, for me. It seems to me the video signals from the image sensors are routed to the FPGA (PLD? technically?), then altered, in some fashion, and then sent to the memory buffer board. Maybe I'll post the schematics, below.
I have a rough idea of what I want, and have sort of block-diagrammed it out, but by limiting myself to DIP packaging I can only find 8 or 16 KB of DP-RAM, per chip. For a 65816, that's alot of chips to fill the mem space! (1,000).
Barry Brey's "Intel microprocessor" textbook mentions "Shared Bus Architecture" (or some such acronym-inducing catch phrase), that had me briefly envisioning 5 or 10 QTY 65C02s fetching data from the dual-port RAM, (maybe doing a little bit of minimal computation?) and shuttling it to some "main memory" (DRAM? ASRAM/"fast"-RAM), and, maybe, even use a 65816 to do the main processing of this "main memory". Just a brief flutter of a thought.
Ideally, I would use the right tool for the job that must be done, but I'm afraid the bewildering plenty of IC design has left me to cobble together a solution that seems "accessible" to me. Hence, the 65xx (despite its "dinosaur", ancient attributes).
OK, enough babble, for today. Here is a schematic or two.
(Note, looking at the Dev-Board/Kodak schematic, I note something I missed before. The PLD handles the sysclk (generated by crystal) and makes?/passes-on? the mclk that runs the sensors; mclk, from the KAC9628 documents is the generator of the pclk and vsynch and hsynch; so, its important. )