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I'm not sure if the "tick" refers to an entire cycle or just the time that phase 2 is high. Maybe someone else has an answer. Sometimes they're also called "T states" or "clocks." I personally don't like to use the word "cycles" because in the language of some other processors, a cycle may be a set of 4, 8, 12, or other number of down-up cycles of the clock source. With the 6502, they're the same thing, so 1 cycle is 1 microsecond (not 4 etc) at 1MHz.
For the first half of a 6502 cycle, phase 2 low. For the second half, phase 2 is high. The duty cycle has to do with the ratio of low time to high time. Ideally, they'll be equal, or close to it. If one is considerably shorter than the other, it will start limiting the maximum operating speed of the processor. There is seldom a good reason to have the duty cycle much above or below 50%. If you have a 1MHz clock (which is a small fraction of the maximum speed of modern 6502's) and phase 2 is low 500ns and high 500ns, you have 50% duty cycle. Note that the term is not "duty cycles," and that you can measure duty cycle with a single cycle of down-up.
The processor does various things internally in the first half of the cycle, when phase 2 is low. One is to set up the address bus and R/W\ line with enough time that they will be valid and stable before phase 2 goes up. After phase 2 goes up, it will take several nanoseconds for RAM-select logic, for example, to get the "all ready" signal through to the RAM's CS input pin. This time is the logic's propagation delay. After that, it will take some time for the RAM to respond and get valid, stable data on the data bus (assuming, for the example, that you're reading the RAM). This time is the memory's access time. (Actually, if you look at the timing diagrams, you'll see other things that could be considered access time for other configurations, but this one will typically be one of the most important ones for a 6502 system.) The data must be valid and stable a certain amount of time (like 10ns) before phase 2 goes down, in order for the processor to latch onto it without errors. That's the processor's data-read setup time. So you see three major timings that must be considered that must fit within the time that phase 2 is up in the last half of a cycle. The memory's access time will normally be a lot longer than the other two.
I should mention here that I've seen some projects where people didn't use the phase 2 signal in the RAM-select glue logic, and then they wind up with problems, sometimes that the computer won't work at all. The problem is that there are times when phase 2 is low that R/W\ could be low when an address you don't want to write to is on the address bus. For reliable operation, your RAM-select logic must wait for phase 2 to go up before making the RAM CS\ input true, in order to make sure that the address and R/W\ lines are valid and stable first. And for the same reason, the logic must de-select the RAM when phase 2 goes down.
Usually the maximum propagation delays, setup times, or access times will be the ones you need to plan around in order to get reliable operation. If you want to push your luck, you can hope that the actual parts you get to put in your circuit meet not only the typical delays, but are even near the minimums. The times for any given part will normally be slower at high temperatures and lower power supply voltages.
You do not have to add a gate's output slew rate to the propagation delay times. It's already included. However if your capacitive loads loads are heavy, you need to be aware that those slew rates will increase. A data sheet for a 74HC00 for example may include propagation delays for 15pf load and a 50pF load. From those you can more-or-less extrapolate how much of the delay is in the gate itself and how much is from the slew rate, and then figure how much longer it may get if you have, for example, a 100pF load (which is probably heavier than you'll have on a simple 6502 project).
As a parenthetical note, I might add that there may be a hold time too which was not mentioned above, where the data has to remain for a little while after the clock goes down; but that's not normally a problem in a simple 6502 system because it will take awhile for the RAM (or whatever is putting data on the bus) to turn off its outputs and go to high impedance, and the capacitance on the bus will hold the data until something else asserts new data.
To directly answer one of your questions, the propagation delays and other timings are very important; although if you run at the snail speed of 1MHz, you'll hardly find logic and memory that's not fast enough for the job.
The above paragraphs describe only part of what happens in one cycle. As Daryl pointed out, there will be one of these read operations to get the op code of your example LDA abs, another for the low address byte, and yet another for the high address byte. The fourth cycle is where the address mentioned by that operand is actually read. The instruction starts with an op code, and usually has an operand following the op code. In the case of the 6502, operands are always one or two bytes.
Most 6502 instructions do not merge op code and operand in the same byte. The 65c02 instructions BBS, BBR, SMB, and RMB are slight exceptions to the rule in that the part of the operand that specifies which bit to operate on is included in the op code.
> Firstly the other post I wrote can be ignored - that was kinda silly of me to post that..
Remember you can edit or delete your own posts. I have edited my own a few times after realizing that something I said could be misleading. It would also be good for forum "housekeeping," so future readers looking through the archives for certain information don't have so much extraneous stuff to slow them down. If you have four questions about clocks, it would be best to put them all under one subject (Hardware -> clocks).
Garth
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