I'm working on building my own homebrew computer, and I want to base it on the MOS 6510. I noticed on the 6510 datasheet that it is possible to run this chip at 3 MHz, though I've never seen it done at more than 1MHz. Has anyone tried to run it at 3 MHz?

I've never seen it done, but I do know that the Commodore 128's 8502A CPU (basically a version of the 6510A with a 6-bit I/O port instead of a 5-bit I/O port) runs at 2MHz when you turn the VIC-II chip's video off...

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Samuel A. Falvo II

Also didn't the BBC Model B run at 2Mhz too?

Actually, the speed of the 8502 has nothing to do with whether the VIC-II is "off" or "on." It so happens that a bit in register $30 of the VIC controls the clock speed of the 8502. That bit, however, has no effect on the VIC itself. Setting a different bit in the same register can cause the VIC to stop refreshing the screen and also stop making memory accesses. If running in 128 mode, the jiffy IRQ will also cease. The result is the 128 will run slightly faster regardless of which clock speed has been selected.

Also, both the 6510 and 8502 have an 8 bit I/O port. However, not all of the bits were actually wired into the motherboard. In the C-64, the 6510's I/O port was used to determine what was visible in the ranges $A000-$BFFF, $D000-$DFFF and $E000-$FFFF. In the C-128, the 8722 MMU handled memory mapping while running in 128 or CP/M mode. In both cases, control of the cassette recorder is also through that port. In the case of the C-64, only five bits were needed to manage memory and the cassette.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Not sure why you'd want to use the 6510 when the 65C02 can be run much faster, has a more flexible programming model, and doesn't carry all the traditional 6502 baggage that the 6510 faithfully duplicates. Also, the 6510 has funky clock requirements. You can clock the 65C02 with a crystal oscillator, which has plenty of drive for both the MPU and other hardware.

Currently available 65C02s (from WDC) are officially rated at 14 MHz when VDD is five volts and can be safely run to as high as 20 MHz. Why consider really old technology (6510) when you could be using just somewhat old technology (65C02).

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I want to see proof of this. My understanding of the DEN bit of the VIC-IIe controls not only the video refresh, but also the CPU speed. This is why you cannot run the 8502 in 2MHz mode while displaying a 40-column screen full-time (you can during borders and sync, but that's it).

The reason is that the VIC-IIe is phase-locked against the CPU (more precisely, vice versa, but who's counting?), since the VIC-IIe uses phase-1 of the bus. Driving the CPU at 2MHz would alter the VIC-IIe timings so far out of NTSC spec that you wouldn't be able to see anything anyway.



False. While the register itself is 8-bits wide as far as software is concerned, under no circumstances are all pins actually brought out to the real-world in either part. I encourage reading the pinout diagrams for both chips to prove it to oneself.



I'm not sure to whom this part is addressed.

Wow, it has been many months and I didn't catch this until now.

Why not use something that's in production today (the 65c02), is a whole lot faster, has all the NMOS bugs fixed, has more instructions and addressing modes, can use a simple RC for a reset circuit due to its Schmitt-trigger input, has an on-board oscillator so you could go with as little as an RC if timing isn't critical, can even have its clock stopped without losing data, has extra inputs and outputs, uses far less power, etc.? Or, for another buck, you can go to the 65816 with wider registers, even more instructions and addressing modes, more vectors, and is easier to program for anything wider than 8-bit quantities?

Its interesting you should talk about the C64 since for last couple of days i have been trying to get a little piece of software running on the Oric rather than its intended machine, the C64.

The software is Electronic Speech systems routines and data for the 1983 game Impossible Mission.
It generates voice synthesis onto the SID's Master volume register. My idea is to use the 6522 to create a virtual register (virtual in that just writing anything will instantly send to AY) on PortA of the AY8912's volume register A (i have done this before).

And yes i know only too well the AY's volume output is log and the SID's is linear but i am hoping that won't make too much difference to the speech quality.

Anyway the code relies on the CIA to provide Timer operations with software controllable stop/start events. However on the Oric we don't have a CIA but only a VIA (6522) so i have been trying to rack my brains into understanding how to convert the code. For speech timings are more critical.

I think the C64's CIA connects to the 6510's NMI line so providing a different IRQ address than the normal IRQ. Unfortunately the Oric only appears to use the NMI line as a soft reset so thats another obstacle i need to get over.

The C64 has two CIA chips: one is connected to IRQ, the other to NMI. I forget which one is which at the moment, and I'm much too tired to look it up now. But, details are available on the web if you peruse long enough.

As far as linear-vs-log, it'll probably badly distort the audio. However, if you de-linearize (versus linearize) and oversample accordingly, I'm sure you can get comparable audio output.

From Mapping the Commodore 128:

53296 $D030 CLKRATE

Processor clock rate control register

Bit 0: This bit controls the processor clock speed. (Remember, the VIC chip is the source of most of the system's timing signals.) When the bit is set to %0, the processor operates at its normal 1-MHz rate. To be precise, the clock frequency is 1.02273 MHz for NTSC (North American) systems and 0.98525 MHz for PAL (European) systems. Setting this bit to %1 doubles the clock rate, providing what is commonly referred to as 2-megahertz (MHz) mode. This is also known as fast mode, the old standard speed being disparagingly referred to as slow mode. During the reset and RUN/STOP-RESTORE sequences, the IOINIT routine [$E109] sets this bit to %0 for slow mode. Fast mode does have a few limitations. While the 8502 microprocessor and the VDC 80-column video chip have no problems operating at the higher clock rate, most of the other I/O chips cannot keep up at this speed. The VIC chip itself cannot maintain its video display at this speed—the 40-column screen becomes a colorful pattern of rapidly flashing squares. It is common practice to set bit 4 of the VIC register at 53265/$D011 to %0 to blank the 40-column screen display while operating in 2-MHz mode. For example, the BASIC routine for the FAST statement [$77B3] includes this step. The VDC provides an alternative to the VIC for fast mode, but other I/O chips have no substitutes. In these cases, the system employs an elaborate technique known as clock stretching, where the clock period is extended to create an effective 1-MHz rate for the portion of the clock cycle when the I/O chip is being accessed.

Because some serial bus and tape communications routines depend on software loops for timing functions, the system is usually switched to the slower clock frequency when serial bus or tape operations are being performed. The contents of this register are stored in location 2615/$0A37 during the operation, and restored to the register when the operation is completed. You can prevent this by setting bit 7 of the custom mode flag (location 2618/$0A3A) to %1. In this case, the clock rate will not be changed during tape and serial operations.

Bit 1: This bit is described in Commodore literature as a test bit. The IOINIT routine [$E019] sets the bit to %0, and no other 128 ROM routine changes that setting. Some programmers have discovered that setting this bit to %1 will blank the 40-column screen display, and have even used this as an alternative to clearing bit 4 of location 53265/$D011 when switching the processor to fast mode. While this does appear to work without side effects, such undocumented "features" are best avoided.

Now, the above was written in 1985 before the full extent of the C-128 hardware had been explored. The author (Ottis R. Cowper) was mostly working from Commodore literature, and his own experimenting to see what was what. I too was able to get the early developer docs for the 128 and in passing, learned from Fred Bowen that setting bit 1 of register $30 not only blanked the display it shut down the VIC to the extent where all it did was DRAM refreshes. Because the VIC was no longer accessing RAM to maintain the 40 column display, the 8502 had unrestricted access to the address and data buses, and thus got more done when measured against wall clock time. My own experimenting subsequently determined that the 8502's effective throughput increased about 8 percent in pure compute-bound processing.

A side-effect of setting bit 1 in register $30 is that the VIC will stop generating raster interrupts, which in the 128 are the source of the jiffy IRQs that, among other things, call the keyboard scanning routine. In other words, setting this bit from an immediate mode POKE would appear to crash the machine, since the required POKE to reverse the process could no longer be entered. This effect is easily observed by putting a logic probe on *IRQ and observing the cessation of activity when bit 1 is set.

I'm probably the worst person for you to argue with about the C-128 hardware. May I suggest that you stop by http://www.commodore128.org sometime and look for postings by BigDumbDinosaur? Also, if you have a real C-128 (or 128D), not an emulator, please try out Clock-Calendar 128 and 80 Column Display Manager so you can get a taste of just how much I might actually know about the C-128 hardware.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I think you're taking my response too personally. I wasn't attempting to insult you. I was merely asking for proof of your claims, as it is contrary to literally everything I've read about the 128 up until now.

(I will say, however, that I'm about the worst person you can argue with w.r.t. the 6510A and 8502A CPUs. )

I do not have live hardware, and likely never will -- there's just no point in it now.

Both of those programs work fairly well in WIN-VICE, although the VDC emulation isn't exact, among other things.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!