First project, could use some advice.

[jzaun]

Hi,

I'm designing my first 6502 computer. The goal is really that the project is fully DIP based so it can be bread boarded and that the resulting computer is simple enough to get used to programming a 6502. I do not just want to build a computer someone else designed as I would like to learn the whole process. I'd like it to be expandable so I can learn some other hardware as well. This really is a stepping stone into building a 65816 based computer down the road. But I figured baby steps first.

With that in mind I came up with this as a memory map and basic hardware for the PC (minus all the glue logic, clock, etc). I would very much appreciate any advice, comments, concerns, criticisms, etc.

Thanks,
Jusitn

Code: Select all

      a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00
0000   0   0   0 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
2000   0   0   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
4000   0   1   0 | 0   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 1 (DUART, ST16C2450IQ48-F)
4800   0   1   0 | 0   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 2 (RTC, M48T02-70PC1)
5000   0   1   0 | 1   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 3
5800   0   1   0 | 1   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 4
6000   0   1   1 | 0   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 5
6800   0   1   1 | 0   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 6
7000   0   1   1 | 1   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 7
7800   0   1   1 | 1   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 8
E000   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 (256K EEPROM, AT28C256-15PU)
FFFE   1   1   1   1   1   1   1   1   1   1   1   1   1   1   1 | 0 (Debug, two SN74HC573ANE4 & LTS-4301JR)

AS6C6264A-70PCN
http://www.mouser.com/ds/2/12/AS6C6264A-10539.pdf

ST16C2450IQ48-F
http://www.mouser.com/ds/2/146/st16c245 ... 221851.pdf

M48T02-70PC1
http://www.mouser.com/ds/2/389/CD00000520-470949.pdf

AT28C256-15PU
http://www.mouser.com/ds/2/36/doc0006-16013.pdf

SN74HC573ANE4
http://www.mouser.com/ds/2/405/sn74hc573a-445143.pdf

LTS-4301JR
http://www.mouser.com/ds/2/239/S_110_S4301JR-595592.pdf

[barrym95838]

Hi, Justin

It seems that your EEPROM would start at $8000, not $E000, based on your binary address map.

It seems that you're trying to put an I/O port at the very top of memory, which would clash with the 6502's IRQ vector. If you don't need IRQs, or if you only use the port for output, I suppose it could work, but it's still a bit unusual.

Mike B.

[GARTHWILSON]

Welcome. Be sure to read through the 6502 primer which addresses pretty much all the aspects of building your own 6502 computer. It is indeed a primer, not a tutorial. A tutorial says, "We're going to build this thing the way I say, and I'm going to hold your hand through it." The primer says, "Here are the basics you need to know to do it your way." It covers a lot of beginners' mistakes and shows you how to get more functionality with less work and parts. The chapters are organized in a logical progression.

As far as breadboarding (meaning wire-wrap or soldered in some kind of perfboard, not solderless socket strips), there are PLCC wire-wrap sockets (which aren't any bigger than the soldertail version), but they're expensive. There are also SOIC-to-DIP adapters you can use if there's a part you want that's only available in SOIC but you want to plug it into a DIP socket.

In your address chart above, I think you'll want your 32Kx8 EEPROM to start at address $8000, not $E000. Remember that the super-fine-grained address decoding (like to pick just two addresses rather than a range) will take more propagation delays, reducing maximum clock speed.

[BigDumbDinosaur]

First off, welcome to our 6502 world.

jzaun wrote:

Code: Select all

      a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00
0000   0   0   0 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
2000   0   0   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
4000   0   1   0 | 0   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 1 (DUART, ST16C2450IQ48-F)
4800   0   1   0 | 0   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 2 (RTC, M48T02-70PC1)
5000   0   1   0 | 1   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 3
5800   0   1   0 | 1   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 4
6000   0   1   1 | 0   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 5
6800   0   1   1 | 0   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 6
7000   0   1   1 | 1   0 | 0   0   0   0   0   0   0   0   0   0   0 I/O 7
7800   0   1   1 | 1   1 | 0   0   0   0   0   0   0   0   0   0   0 I/O 8
E000   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 (256K EEPROM, AT28C256-15PU)
FFFE   1   1   1   1   1   1   1   1   1   1   1   1   1   1   1 | 0 (Debug, two SN74HC573ANE4 & LTS-4301JR)

Are you really planning to connect eight different I/O devices?

Quote:

ST16C2450IQ48-F http://www.mouser.com/ds/2/146/st16c245 ... 221851.pdf

That device is a pair of 16450 UARTs in one package. The 16450 is pretty lame as UARTs go—the PC world dumped it 25 years ago in favor of the 16550 and later. Do you really need two channels? If not, you may be better off looking at the 65C51 as a "get started" UART. If you do need dual channels, my recommendation would be to go with the NXP 26C92 or 28L92, or the Exar compatibles if your heart is set on using an Exar device.

Also, as Mike noted, you are usurping the IRQ hardware vector by attaching your 7-seg display there. That would eliminate any possibility of using IRQs to handle I/O.

[jzaun]

Thank you all for the replies. It's nice to find a community the is helpful and welcoming to new people. I feel a bit of an idiot, I did have my memory address wrong for the EEPROM, $8000 is the location shown not $E000. I'm not sure how I missed the IRQ vector, I was reading the primer and the datasheet.

BigDumbDinosaur has a good point, I'm not really looking to hook up 8 I/Os at the same time on this. I really just want to be able to play with some things to learn them and I can do that one at a time.

So the changes I made were to remove four of I/O slots and to move my 7-seg leds up to $7000. I can always remove them and add something else if needed later on. The reason I wanted them was to be able to output something before the uart was configured. I'm mainly a software person and love lots of debug output to help track down issues

So with the comments taken this is my revised memory map:

Code: Select all

      a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00
0000   0   0   0 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
2000   0   0   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
4000   0   1   0 | 0 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 1 (DUART, SC28L92A1A,529)
5000   0   1   0 | 1 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 2 (RTC, M48T02-70PC1)
6000   0   1   1 | 0 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 3
7000   0   1   1 | 1 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 4 (Debug, two SN74HC573ANE4 & LTS-4301JR)
8000   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 (256K EEPROM, AT28C256-15PU)

BigDumbDinosaur mentioned that the ST16C2450IQ48-F) is a bad choice for a DUART. I would like to stick with 2 UARTs, one for a serial connection to my laptop and one to have another device with. I was thinking of trying PICASO down the line.

I picked the in because it was from Exar and they make the XR16L788IQ-F that I thought would be interesting to play with one day down the line in other projects. I may be naive but I figured two devices from the same manufacture would be similar enough that knowledge learned on one might transfer to another. That being said I'm not against using a different DUART but would like to keep the DIP package which leads me back to the ST16C2450IQ48-F (at least on mouser.

(googling)

Showing how little I know, I didn't even realize there were different kinds of UARTs. I found this explaining the 16450 and 16550. I see how the 16450 is rather lame. At this point I'm leaning towards the SC28L92. The PLCC-44 isn't bad but a DIP package would be much easier. Wish manufacturers made more things in DIPs.

Any other advice, comments, etc. with the modifications to the memory map?

Thank you again for replies and being so helpful to a new person

- Justin

[BigDumbDinosaur]

jzaun wrote:

So the changes I made were to remove four of I/O slots and to move my 7-seg leds up to $7000. I can always remove them and add something else if needed later on. The reason I wanted them was to be able to output something before the uart was configured. I'm mainly a software person and love lots of debug output to help track down issues

You could fine-grain your I/O decoding a bit with relatively simple circuitry and considerably reduce the address footprint used by your I/O, viz:

Compact I/O Decoding

The above decodes eight I/O devices into pages, so the first device appears at $D000, the second at $D100, and so forth. Worst-case prop time at 5 volts is 14ns from the time the MPU asserts an address until one of the eight possible devices sees a chip select. I have a slightly enhanced version of that in my POC unit, which is stable at 14 MHz.

Quote:

Code: Select all

      a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00
0000   0   0   0 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
2000   0   0   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0 (64K SRAM, AS6C6264A-70PCN)
4000   0   1   0 | 0 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 1 (DUART, SC28L92A1A,529)
5000   0   1   0 | 1 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 2 (RTC, M48T02-70PC1)
6000   0   1   1 | 0 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 3
7000   0   1   1 | 1 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 4 (Debug, two SN74HC573ANE4 & LTS-4301JR)
8000   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 (256K EEPROM, AT28C256-15PU)

Why not give it more RAM? 32KB of ROM seems a bit much for most 6502 systems.

Quote:

BigDumbDinosaur mentioned that the ST16C2450IQ48-F) is a bad choice for a DUART. I would like to stick with 2 UARTs, one for a serial connection to my laptop and one to have another device with. I was thinking of trying PICASO down the line.

I purchased one of the Picaso modules a few years ago, but decided that it would not make a good console display, mainly due to the lack of a hardware-generated cursor and an idiosyncratic programming model. It would be good for a kiosk type display, especially if using a touch screen. I ended up giving away the module.

Quote:

At this point I'm leaning towards the SC28L92. The PLCC-44 isn't bad but a DIP package would be much easier. Wish manufacturers made more things in DIPs.

Relatively complex I/O chips like the 28L92 become quite bulky in DIP form. You haven't gone into any detail on just how you are going to construct your unit. If you are going to wirewrap or use a PCB, PLCC-44 is just as build-friendly as DIP, and takes up less space. When I laid out my POC unit I tried it with DIP and PLCC-44 packages for the MPU and DUART. I went with PLCC due to a substantial reduction in overall footprint of these two devices.

[mkl0815]

Welcome Justin,

if you want to start on a breadboard, you can start with a simple decoding logic that at the beginning only provides the things you really need.
Just RAM, EEPROM and some UART. Don't worry about wasted memory ranges during the first steps.

If you design your layout on the breadboard in a clever way, you can replace the glue logic without changing the rest of the circuit. I had the glue logic on a second breadboard during my first steps.

Mario.

[jzaun]

So one last tweak, I hope, to give myself a little more RAM and a little less ROM. Both the chips are 256K so I can mess with the amount of RAM/ROM I have in the future but I think this should be fine to get me up and running.

Code: Select all

      a15 a14 a13 a12 a11 a10 a09 a08 a07 a06 a05 a04 a03 a02 a01 a00
0000   0 | 0   0   0   0   0   0   0   0   0   0   0   0   0   0   0 (256Kbit SRAM, AS6C62256A-70PCN)
8000   1   0   0   0 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 1 (DUART, ST16C2450IQ48-F)
9000   1   0   0   1 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 2 (RTC, M48T02-70PC1)
A000   1   0   1   0 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 3
B000   1   0   1   1 | 0   0   0   0   0   0   0   0   0   0   0   0 I/O 4 (Debug, two SN74HC573ANE4 & LTS-4301JR)
C000   1   1 | 0   0   0   0   0   0   0   0   0   0   0   0   0   0 (128Kbit EEPROM, AT28C256-15PU 256Kbit chip)

This would be the logic for the above map, hopefully it looks OK. The timing works out to 11ns for I/O, 8.4ns for RAM and 4.2ns for ROM.

6502.org wrote:

Image no longer available: https://www.dropbox.com/s/zudni8ddzhrho1e/Memory%20Map.png?raw=1

I would be able to connect A11 to the decoder if I wanted more I/O in the future. Anything drastically wrong with this setup? If not this is what I'll go with.

- Justin

[rwiker]

The data sheet I'm looking at has 74F11N as a triple AND gate - the corresponding triple NAND gate is the 74F10N.

[barrym95838]

jzaun wrote:

This would be the logic for the above map, hopefully it looks OK. The timing works out to 11ns for I/O, 8.4ns for RAM and 4.2ns for ROM.

I would be able to connect A11 to the decoder if I wanted more I/O in the future. Anything drastically wrong with this setup? If not this is what I'll go with.

- Justin

Uh, it's been a few decades since I made a 65xx breadboard project, but I think that you'll just need A15 to select your RAM, and your decoder to divide the remaining 32K into 4K chunks, pretty much eliminating the NAND from consideration, unless you need it for other stuff. So, the select timing for your RAM is the speed of light in copper times the length of the wire between A15 and your chip select.

Mike B.

[Edit: whoops ... that would be length divided by c, not c times length!]

[floobydust]

First, welcome to the forum!

Second, not to try and over simplify this stuff, but coming up with yet another memory map for the 6502 is not exactly a difficult or thought provoking exercise. If you look at all of the commercial machines from Apple, Atari, Commodore, OSI, BBC, etc. and then think of all of the video games done around the 6502, I tend to think pretty much every conceivable map has been done to a large extent.

Having said this, I'll simply say that some of the sites linked from here like Garth's, BDD's, Daryl's and others tend to cover it very well. You can also look at the latest SXB offerings from WDC and get some additional ideas. As there's only 64KB of addressing, there are limits. I'm still using the same memory map I did back in the late 80's. It dirt simple.... 32KB of RAM from $0000 - $7FFF and 32KB of ROM from $8000 - $FFFF, less an I/O page of 256 bytes located at $FE00 and decode that into 8-I/O selects that are 32 bytes wide each. This gives plenty of flexibility for interfacing lots of I/O devices and can still be very quick on clock rates.

I'm now using 74HC logic for the glue chips (3 in total) and have had a board set running at 10MHz for about 18 months now and it's been completely reliable. The main reason I opted for a single page for I/O was to maximize the amount of RAM and ROM in the system and provide better flexibility going forward. You might even want to think about a single programmable glue chip to simplify the design further, should you have the bits and pieces to manage that.

[BigDumbDinosaur]

rwiker wrote:

The data sheet I'm looking at has 74F11N as a triple AND gate - the corresponding triple NAND gate is the 74F10N.

That's correct. Better yet would be to use a 74AC10, which has about the same performance as the 74F10, but with lower power consumption, greater fanout and a slightly lower cost.