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PostPosted: Thu Nov 26, 2015 10:52 pm 
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sark02 wrote:
Still, the point being that you could use the FPGA to implement an MMU and, as extra credit, custom instructions to manage it (as opposed to having a memory mapped interface). All with a stock 65c02.

If you're going to the trouble of using an FPGA, you may as well do everything on it as Rob already suggested. But I prefer to limit myself to older technology for this particular project.

sark02 wrote:
Which ever way you go, it sounds like a fun little project. Good luck!

Thanks.


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PostPosted: Thu Nov 26, 2015 11:01 pm 
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BigDumbDinosaur wrote:
Also possible, I would think, would be synthesizing the function of the '612 in a 22V10 GAL.

Unless you know of some tricks I don't know of, I don't see how this would be possible. First of all, the '612 is a 40-pin device and the 22V10 is a 24-pin PDIP. Second of all, as far as I know, the 22V10 only has 10 flip flops on it which is not nearly enough state. You'd probably need something like 64 macrocells just to implement the simple MMU I describe at the top of this thread -- 32 for the memory alone.

BigDumbDinosaur wrote:
The trouble with using old silicon like the '612 is performance tends to be lackluster, fanout may be weak and the available sources may be dubious in nature. In particular, buying chips off eBay runs the risk of being sold a counterfeit.

No disagreement here. I'll pick up a couple to try, but I would like to experiment more with the idea I've presented as well as I think it may even be fast enough for a 14 MHz system.


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PostPosted: Thu Nov 26, 2015 11:15 pm 
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Aslak3 wrote:
My project (PCB stage) includes a 6809 and a couple of Altera Flex10K to implement a bus stealing DMA controller and a simple 4K/16 page MMU, as well as other functions. I am consciously limiting myself to through-hole, 5V parts.

I'm consciously limiting myself to parts available in DIP format, or at least easily converted to DIP format.

Aslak3 wrote:
jmp(FFFA): I agree with a lot of what you've said. Part of the attraction with using a discrete, "retro" CPU with a modern PLD is to replicate what a state of the retro-art 1980s micro would have achieved with a bunch of ASICs. Something like the Sam Coupe, C64, or even the Amiga. Working on a similar design with everything embedded in a contemporary FPGA feels quite different to me.

There are quite a few projects out there (MiniMig, etc.) where people reverse engineer a complete system from the 1980's and then implement part or all of the system using an FPGA. I admire the skill involved, but don't feel moved to go in this direction myself at the moment. BTW, have you seen this thread: http://forum.6502.org/viewtopic.php?f=4&t=3500?

It's great to hear that I'm not the only 6809 fan here. It shares significant lineage with the 6502, too.


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PostPosted: Fri Nov 27, 2015 3:51 am 
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BigDumbDinosaur wrote:
That's an important point. 65xx programs are not huge like what you see in the x86 arena. I've written some really big 65xx programs over the years, but only once or twice exceeded 16KB code size.

If you're programming the x86 in 16-bit real mode, the code density is very high -- much more so than even a 65c816. By way of example, have a look at this 125-byte long program to calculate the first 9304 digits of Pi: http://www.boo.net/~jasonp/pi_com.uu. If there's interest, we could start another thread in the Programming section to follow up on this.


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PostPosted: Fri Nov 27, 2015 4:11 am 
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jmp(FFFA) wrote:
... have a look at this 125-byte long program to calculate the first 9304 digits of Pi: http://www.boo.net/~jasonp/pi_com.uu. If there's interest, we could start another thread in the Programming section to follow up on this.


In the hands of a master like dclxvi, the NMOS 6502 can do something similar in about 130 bytes, but I agree that 8086 code is impressively dense. [double entendre, anyone? :wink: ]

Mike B.


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PostPosted: Fri Nov 27, 2015 9:06 am 
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... and Bruce didn't have the advantage of MUL or DIV instructions!


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PostPosted: Fri Nov 27, 2015 1:09 pm 
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barrym95838 wrote:
In the hands of a master like dclxvi, the NMOS 6502 can do something similar in about 130 bytes, but I agree that 8086 code is impressively dense. [double entendre, anyone? :wink: ]

That is an impressive bit of 6502 code! It would be interesting to see how many bytes an x86 "master" could translate it into. I guess it would vary inversely with his personal density. :D


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PostPosted: Sat Nov 28, 2015 1:34 pm 
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jmp(FFFA) wrote:
That is an impressive bit of 6502 code! It would be interesting to see how many bytes an x86 "master" could translate it into.

Out of curiousity, I did a little searching and found this: http://www.boo.net/~jasonp/bf3pi.zip which does it in 40% the size of the 6502 code (52 bytes)!

Back on topic: I'm going to complete the design for the MMU presented at the top of this thread by defining the logic equations for the GAL. Then it'll just be a matter of building up a new system on breadboard for testing as my previous 65c02 system (http://forum.6502.org/viewtopic.php?f=4&t=3476) has already grown too large to fit this onto. Given the lack of availability of sufficiently large breadboards, I may have to build one up myself similar to what Brad has done for his Vulcan74 project (http://forum.6502.org/viewtopic.php?f=4&t=3329).


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