I use JPEGs for that kind of thing, but set the quality for 100%. That gets rid of the artifacting, but it still gets decent compression since there are so many pixels in a row that are exactly the same color. Here's one that definitely won't cause any worries about giving away any company secrets, showing the top side's copper of an extremely simple postage-stamp-sized board:

The file is only 18K in size.


With its flat face facing you, and pins pointed down, it's E-B-C.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The .PNG format is lossless, and does a good job of compressing typical PCB patterns. It's similar to .GIF but with modern features, and free of patents. Here's GARTHWILSON's image, but converted to PNG, now only 7KB (it probably would have been a bit smaller when made directly from the original bitmap. Now it's trying to compress the small JPEG errors).

The patent on the LZW compression algorithm used in GIF expired in 2003, and all other patents related to GIF expired in 2004.

GIF images can be animated, whereas PNG images cannot. However, PNG offers much better color rendering. For Internet usage, GIF is generally adequate when high color accuracy is unimportant—I routinely use GIF for anything other than photographs.

Versions of Microsoft's Internet Explorer prior to 7.0 don't support PNG and there are problems with PNG in versions 8.0 and 9.0 (however, you shouldn't be using any version of IE if you know what's good for you). PNG is well-supported in most other browsers.

Decisions, decisions...

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I am afraid its slightly worse than that, Garth. (Do I dare confess?). For a fella who wants to learn electronics, I am not very good with transistors! HA! Quite a confession!

I know a fair amount about the history, and even quite a bit about the theory of transistors; but PRACTICAL info! REAL info about how to use them! Forget about it!

I am out of practice on the whole "NPN", "PNP" thing. Some of it is my fault (i.e. lazy; my excuse? Biologist!), but I also blame history and physics! History, since it involves "people", is complex and foolish; physics, since it exists quite separate from the human mind's conception and perception of it, is complex and hidden.

Cryptic comments, you say! YES. I will explain. Conventional current is stupid, and always confuses me. Maybe an engineer from the 6502-forum could set me straight? So, when does positive mean "excess of electrons"? On which schematics? Old? New? Never?

(Technically, I don't care if the electrons are "jealous" and the protons are "vengeful"; so long as they are ALWAYS jealous and vengeful, respectively, and never switch places. I mean, positive and negative are just words, and just as easily can be applied in the opposite fashion. I mean, who could truly complain? Transistors! That's who!)

So, my understanding is that, historically, engineers used + to mean that electrons would flow from that lead, through the circuit, to ground. Is this STILL true, of engineer schematics? I think scientists have ALWAYS used the convention that electrons are negative? Am I wrong there?

So ground is, essentially, neutral, or, rather, a good "electron sink". But, wait? Ground is also, a good source of electrons, is it not? (I almost need a meteorologist book to remember what lightning is? But, doesn't lightning have currents that flow up in order to meet the currents flowing down?)

My physics book says that Voltage = Electrical Potential Energy per unit charge. (i.e. delta-W/electron, I think?). Voltages, as measured with leads, is relative. But, perhaps the silicon, phosphorous, and boron atoms do not "believe" in relativity (relativity of voltage)? Perhaps, THEY "know" what ground state is!

So, I do have the pin diagram for the single transistor, but it recommends a negative voltage, leaving me scratching my head in embarrassed confusion? My "wall wart", 6V AC-to-DC converter (is it 300mA rating? I forget?) feeds into a 7805, with a couple of electrolytic capacitors in the circuit, giving my project board what I have, thus far, considered to be a stable source of +5 volts, and a decent GND rail. Has my reason failed me, so far?

OK, I have rambled WAY TOO long on this subject; this topic is not immediately relevant to my "6502 madness", but instead is for my fiber optic transmitter/receiver circuits. (Maybe later, I will post my circuit diagrams for that FO project, and you can set me straight on "the fundamentals"). Just know, I have a second circuit that uses a 2N2222 (NPN) instead of a 2907 (PNP), and perhaps I'll just revert to using that one (rather than feebly obsessing over electrons, protons, "the nature of existence" and "the sound of one hand clapping".).

(I guess I shouldn't mock philosophy, or science, since CMOS--its invention and its use--is predicated upon the proper understanding of the movement of electrons and holes. These ideas are essential to proper design and to the functioning of the hardware.).

Moving on to the topic of my "6502 madness", I will post, below this post, the PCB plan, so far. You have my permission to laugh, as I have broken every rule that I know I shouldn't break (very similar to my "9-image-sensor" project, a few years ago). My goals, as always, are (1) construct something that MIGHT work, (2) if it doesn't, try to get it to work and (3) if it still doesn't work, admire it as art, and finally (4) learn something.

(Hey, here is a silly question. How come CMOS chips have only one power and one ground pin? I mean, they don't generally have a + 5V and a -5 V and a GND? I guess, with all measurements of voltages being relative, the NPNs and the PNPs can "split the difference" and find a voltage that "looks" negative to the one type of trans., while "looking" positive to the other? Or is this, too, a foolish question?)

Thanks, all, for the info regarding images and lossy formats. It isn't too often that I ruin an image by not paying attention to "platform portabilty" and file format, but it sure stinks when I do mess things up.

My CAD program is difficult. I am using some "off-the-shelf", Big-Lots/Walmart/Staples/Big-Box-Store, 15$ CAD program; like the same kind they sell to amateur architects, and high school art students (i.e. people who don't know any better and/or can't afford professional tools). The file format choices all stink!

I think I got some good images out, once, but can't quite remember how? Also, I remember forgetting how to do this, once before, and I remember resorting to "screen shots" (i.e. ctrl + "print screen" button) of small portions of the board, copy + paste + save, to bmp, in "windows paintbrush", and then, stitching them all together, like they were some kind of quilt. Pain in the butt!!! But it worked.

If I have to, I will resort to the same, this time around. I am like 70% done with the board. All that is left is the mystery pins, the optional mem. extension (I forgot already is 32MB max address space of 65816? don't answer that? I will look it up again; check my memory map again?), ground and power pins (should have done it first; I even read Garth's primer and ignored the advice to do a "star arrangement"), the OE's, CEs' and WEs, and the 6522 (which I have zero idea how to use!).

Anybody know if I left too much room for input-output? (24KB RAM; 16KB I/O ; 24KB ROM)? Is such a memory map foolish? I thought I would keep it simple; $0000-$5FFF RAM ; $6000-$9FFF I/O ; $A000-$FFFF ROM). Seems reasonable?

So, I definitely need advice on this one question; where do the 65816 address pins attach to the 6522? I mean, they have to, don't they?

(you'll note that, despite the advice I got on the first day I posted here, I am "trying to build/fly a 747, before I've even tried a piper/Cessna/etc.).

Now, the only thing I know for sure about my I/O applications is that they need to be I2C (for my previous Kodak image sensor (9 QTY) focal plane array). But, since that part is discontinued, and other image sensors are both (1) better and (2) cheaper, now, it seems the old project might never function. But, a new FPA project, might be in order! I assume I2C is something of an industry standard, but perhaps, I'll keep an open mind (CCDs used to be the "gold standard" and some scientific applications consider CCDs best... it might be changing though.... I am "out of the loop" ...).

Unfortunately, I am just one person; not like NASA, who gets a team of people to design their FPAs! download/file.php?id=2961&mode=view


Well, so I guess I'll post the PCB (low res, though they are!) pics and offer one parting comment. I am thinking of a ground plane, but I am sure I didn't quite understand Garth's primer discussion of it. I only have a two layer PCB (no internal vias, or multilayer stack) and, though I have some colloidal silver + carbon/graphite solution (for plated through holes), you will be able to see in the pictures little blue-black dots that are the drill holes. I will just snake a jumper wire through and solder to pads on either side. (maybe, if this type of board is unacceptable, I can alter the pattern and try a second time; the second time, I can try my hand at plated through holes. Somebody told me they were tough to do, because of burrs on inside of drill holes, and etc. I can do a plating bath. That shouldn't be too tough!).

I will also have to take a look at the "hardware post" on this forum. I should have done so a few weeks ago!

Whoops; a glitch on my CAD program tends to freeze the program if I label things with letters and numbers. So, no labels on the chips. Sorry; here they are; 65816, (black) front and center (i.e. off-center).

Bottom left green (Cypress) 65256 RAM; Top Left (a few red pin holes/rings) memory expansion socket; ROM (black chip) diagonal Top/Center; Green (slanted, top right) 6522; and bottom right is the 74HC138 (green) and the 74HC11 (3-input AND).

Oh yeah, no reset circuit yet, and no clock yet. Unfortunately, the board is about 11 inches by 6 inches (I think? I forget?). I was hoping for more compact and fewer "jumpers".

Maybe I'll put the pin diagrams up later; if you are a glutton for punishment, you can "check my work". Certainly, the decode circuit will need an extra set of eyes.

Thanks and Cheers!

(If you see " a train wreck" developing, feel free to set me straight (I am stubborn about doing things my own way, but also very yielding to wisdom and experience. The latter is especially true, when I have already tried--and failed--once or twice!).)

responding to three posts up:

I always go with electron flow, not conventional current. The electrons flow to the more positive side. Take for example an NPN transistor, with a beta of 100, its emitter grounded, and it collector connected to a positive voltage. If you pull one electron out of the base (by pulling the base up), it will allow 100 electrons to slip through and come out the collector. PNP is just the reverse. To match the example, its emitter would go to the positive rail, and its collector to a less positive voltage, and then you put an electron into the base to let 100 go into the collector and out the emitter and into the positive rail. (In reality it's not quite so simple, but this works for starters.)

FETs work on different principles. They are voltage-controlled devices, not current-controlled. JFETs are normally on, and reverse-biasing the P-N junction between the gate and the channel builds up a depletion zone which will not conduct, so the channel is narrowed and the amount of current it lets through is decreased, until you reach total pinch-off and it does not conduct at all. This is depletion mode. In the case of N-channel, having the gate at a lower voltage than the source will narrow the channel and reduce the current flow through the channel. In the case of P-channel, having the gate higher than the source will narrow the channel.

MOSFETs work quite a bit differently. I don't understand the physics as well, but I don't have to in order to apply them in a circuit. They are enhancement-mode devices, and normally off. In the case of N-channel, you turn it on by making the gate more positive than the source. P-channel is the opposite.

None of these cases necessarily need a negative supply voltage. You just work the configurations to work within the available voltages.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Typically A0-A3 go to the 6522's RS0-RS3. The two chip selects get fed by address-decoding logic which in turn is fed by higher address bits.

No, you do not need 16KB of address space for I/O; but it makes address decoding simpler, resulting if fewer cascaded levels of logic and shorter propagation delays, which in turn allows higher clock speeds. A beginner in this stuff will have a hard time filling 24K of RAM or ROM.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I see; thanks a zillion! (a zillion? try decoding that! How many bits in a Zilla-byte! Ha ha!)

Sheer curiosity forced me to find the wiki: Positive and Negative Lightning

(three posts up)

So, I should probably think about it as "when the switch closes the circuit (i.e. when I push the button), the electrons travel from the ground, through the circuit elements, towards the positive supply, since the positive supply exerts a force upon the mobile carriers which, in a wire, just happen to be electrons (negatively charged)."?

I always though that is the way I SHOULD look at it, but then I read about "conventional current" and got confused.

I think the wikipedia page has set it down, in fairly clear fashion. (I suppose it wouldn't hurt for me to study power supplies, transformers, and household wioring too! Even, right down to the "bus bars" in the basement!).https://en.wikipedia.org/wiki/Electric_current#Conventions

Thanks. I am sure to keep track of my discrete transistors, their types and functions, and their "beta". I suppose Weste and Eshraghian "Principles of CMOS VLSI" design wouldn't hurt; I'll review. (perhaps a historical study of CMOS is in order? Who did it first? Did I hear a rumor the Japanese had it before I us? I'll have to track down that story!).

I forgot a lot of this stuff, but maybe I could get back into it. I still have the LASI7 IC layout program on my computer! Maybe I'll make that retinomorphic image sensor yet!

Have gotten deeply involved in the PCB design.

Still don't know how to implement power planes or ground planes. I just put one of each, one or two inches square, every few inches on the board (skirting the edges of the board; some unfortunate cases involve long traces--2 inches or more--running close to the planes; maybe bad?). Can't remember if my two-sided copper board should have a power plane on the opposite side of a ground plane, or if it is better to keep ground planes opposite ground planes? Any advice?

Still looking for my book about PCB design; library is a mess. Maybe try the internet for a pdf book on the subject?

OK, have been thinking seriously about 65C22 and the mystery pins of the '816 ( http://forum.6502.org/viewtopic.php?f=4&t=3404 , for the '816, and, in similar fashion for 65C02, the following , http://www.wilsonminesco.com/6502primer/MysteryPins.html ). All that is left in my PCB drawing (and reset and clock circuit; though I have thought those through pretty completely, and merely have to draw them!) is these pins; clocks, interrupts, resets, aborts, and etc..

Still confused by an address coding thing; I forgot to consider adding the Phi2 clock signal. Must cogitate. I will get the right answer eventually. One sticking point? I am using the 65816, so I'm not sure that I need Phi2 in the decoding scheme.

Right now, on the schematic, both my RAM and ROM have OE/ tied to low, i.e. GND plane. I think that is right, since WE/ is tied to the RWB pin on the 65816, and when it swings high, my RAM/ROM chip decides to listen to WE/ and CS/ and ignore the OE/ pin (level).

Have been thinking seriously about my 7 (9?) QTY , KAC-9628, kodak image sensor project. 300 kp (approx. VGA), 30 fps, (8, 10 or 12 bit) digital video output, with I2C bus control and programming. I have a printout somewhere; but library a mess! Maybe I'll print out the ten pages or so of "timing specs" and "video-mode operation; slave and master modes" section. That way, I can read and mark and note-take, at will.

Unfortunately, these sensors run at 3.3 v, which maybe isn't such a bad thing, EXCEPT, the digital output is then 3V too (more like 2.2 V to 3.15 Volts; and 0 to 0.5 volts low). Also, clock max is 48 MHz (25 MhZ normal) and 12 MHz min.. I guess that is OK, since the 65816 can clock as high as 14 MHz (at 5.5 V).

Hey! maybe I could run the '816 at 3 volts? But then the RAM/ROM and everything else might be wrong? I dunno? I should stick to 5V for 65816 and etc....KAC project will run at 3.3 and I will look for solution to lower logic levels? Maybe buffers? Maybe register-chips? register/latch? Maybe a RAM that accepts 3V levels and outputs 5v levels?

Maybe I'll check the 65C22 specs? Do they allow 3 volt inputs and give 5 volt outputs to the '816?

Oh well... too much speculation for Friday night. I will go home, make dinner, watch movie, and study til I sleep!

Here are a few schematics, for posterity's sake!

Oh yeah, P.S. I think I might need more glue logic chips for the extended memory; and I jiust noticed that buying Wilson's extended memory module gives me twice the memory I can address with the 65816 (32MB instead of the 16 MB, "addressable".). Maybe extra won't hurt, especially, if I gather a bunch of data with my "image sensor madness". Perhaps some extra glue logic somewhere could fill up my first 16 MB of RAM and then move to the other 16 MB?

Maybe a mystery pin could be co-opted to some extra address coding/decoding (i.e. for extra memory)? Just a thought... a speculation, really... I don't REALLY understand these things!

What it sounds like you're describing is not a plane. With a plane, every trace, for its entire length, will hover above the plane, hugging it, very close, for its entire length, with no interruptions in the plane. That's not to say every design needs a real plane, as it depends on especially rise times and trace length. If the rise times (ie, slew rate) are not too fast, and traces are short, the behavior will be fine without a ground plane. Even the Ph.D.'s in this stuff don't really agree though on where the thresholds are. Dr. Howard Johnson has a lot of related articles at https://web.archive.org/web/20120302190 ... eyword.htm . I wish I could remember which one had his rules of thumb on it.


I'm not sure what you mean there, but two ground planes on adjacent layers won't accomplish anything. If you have four layers and two planes, make layers 2 & 3 the power and ground planes. If you have six layers, it's usually best to have layers 2 and 5 be planes, and 1, 3, 4, and 6 be signal planes, so every signal layer is next to a plane layer. The power plane should be bypassed to the ground plane at each ground and Vcc pin of each IC. I doubt if you'll be pushing things far enough for these extremes to matter much though. If you want to just always be in the practice of doing it the best it can be without incurring extra cost, go for it. It may pay off nicely later.


If you bring phase 2 into the chip-selects logic, it should usually only be for RAM. Actually (as BDD likes to point out) you can get away with a slightly slower access time if you let the RAM chip select go true before phase 2 rises, and only use phase 2 to enable the WR\ or OE\; but RAM is available in faster speeds than anything else you're likely to use anyway, so it probably won't be the pacing item in terms of speed.


Whether it's ideal or not, without seeing the diagram, it sounds like it will work.


The '816 will work at 3V, but the maximum speed will be less. You won't connect I2C directly to the '816 anyway, but go through an I/O IC, possibly the 65c22. I2C has open collectors anyway, and pull-up resistors to Vcc, and most I2C devices can handle 5V on the I2C. For the W65C22N, the input high voltage is a minimum of 2.0V, whereas for the W65C22S, it's much higher, 3.5 or 4.0 for a 5V power supply, depending on what part of the data sheet you believe. (Yeah, WDC's data sheets have problems!)


The memory module is 4Mx8, which is 4 megabytes, or 32 megabits. It is not 32 megabytes. It has up to eight 512kbyte ICs, which are the most I've seen for 5V. There have been two customers that have ordered four boards at once, in order to get 16MB (128Mb).

Edited: kbit --> kbyte, 28 words from the end

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Before you commit to such an arrangement be sure to carefully peruse the data sheet for correct usage of the RAM control inputs. In some cases, simultaneously asserting /OE and /WE is an undefined operation.

I've been having some trouble following your posts, but gather that you are designing with the 65C816 in mind. The '816 is not as tolerant of haphazard bus management as is the 65C02. In particular, you have to be constantly aware of the use of the data bus to emit the bank address, which occurs when !Ø2 && (VDA || VPA) is true. If your RAM or ROM has its /OE permanently tied low and the '816 is in a read cycle (RWB is high), the RAM or ROM when selected will drive the data bus. If that happens while Ø2 is low (!Ø2), your device and the '816 will be simultaneously driving the data bus, the former with who-knows-what and the latter with the bank address. There's no telling how your circuit will behave in such a case.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!