dolomiah wrote:
Thanks Garth. The current address decoding scheme works fine, but yes I can see how I could eliminate the '138 with your approach. It doesn't compress the IO block unfortunately (I need to keep 4 bits for register addressing, and then 8 for device selection, plus the top 4 bits are needed to select the IO block) - but it would be quicker.
Just to make sure we're communicating: You can still do it. You wanted 4K for the I/O. Use A15-A12 (that's four lines) to select that block, and use A0-A3 (four more lines) for register selects. That leaves A4-A11 (that's eight lines) for device selection, one address line per device. Since your I/O ICs don't have two chip selects like 65xx ones do, although it would take more room, you can reduce the propagation delay time by replacing the '138 with a 2-input gate for each IC, and use one input for the I/O block enable and one for the respective address line.
I don't get too particular about trying to give early address qualification for RAM. SRAM is the fastest of all the major parts we put on the board, available down to 6 or 8ns. Additionally, when you push the limits of a 65c02 (going beyond the specified max), the address is valid and stable almost no time before Φ2 rises anyway. Doing it BDD's way is good practice if the goal is to run absolutely as fast as possible; but I really don't see it making a significant difference when you'll run into speed limits on other things first.