banedon wrote:
BigDumbDinosaur wrote:
Why are you qualifying /RAM_SEL with Ø2?
So that it will only enable the RAM on the rising edge of Ø2. The address decoding scheme is from Gareth's Primer as I wanted a bit of speed and didn't want to us e a decoder or (C)PLD.
Better to enable the RAM when a valid address is present on A0-A15. You are throwing away quite a bit of setup time by waiting until after the rise of Ø2 to enable the RAM.
What you do want to qualify with Ø2 are the read/write signals seen by the SRAM. Qualifying read isn't essential with the 65C02 but qualifying write is, since the data bus may contain random content while Ø2 is low.
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File comment: Read-Write Qualified by Ø2
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The above circuit will work with any 65xx MPU and any RAM or I/O device that has separate /RD and /WD control inputs. It is not to be used with 65xx I/O devices.
Arlet wrote:
No, I was thinking about putting CPU, RAM, EEPROM, VIA (i.e everything connected to the big buses) all vertically, side by side, with the buses running horizontally between the pins, and then put all the other stuff above that. But I have little experience routing these DIP parts, so I'm not sure it will actually work.
That is essentially how I am doing it in POC V2.
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File comment: POC V2 PCB Layout
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In the above illustration, the 65C816 (PLCC-44) is at the right. To the left of it is the SRAM (an SOJ-36 package), then the EPROM, then the "expansion socket" and finally the QUART (PLCC-52). The CPLD (PLCC-44) is immediately above the SRAM and EPROM socket. Signal traces are 6 mils and signal via are 26 mils with an 8 mil hole.
The theory behind this layout is that the device with the most number of bus connections, the SRAM, is closest to the MPU and the device with the least number of bus connections, the DUART, is farthest from the MPU. Trace routing tends to get easier this way. I used the same layout approach in POC V1, which is stable at 12.5 MHz, and a bit wobbly at 15 MHz.