Cypress Semiconductor Corp., who makes very high speed static RAM, disagrees with you

Dr. Johnson replies:

Carl, I like your first approach best (Figure 1a). The idea of sequencing your bypass connections from the VCC plane, to a bypass capacitor, and then to you IC power pin is very old. Those who advocate this approach usually justify the circuit (if there is any explanation at all) as an attempt to construct a filter network with the stated objective of "keeping power supply noise contained at the IC site, preventing it from getting out onto the larger pcb".

In the context of a high-speed digital pcb with solid power and ground planes, sequencing the bypass connection does not accomplish that goal. A power filter by itself does not prevent noise escaping into the pcb. Even if you power your IC from its own internal battery source, without involving the external power system at all, you still can't prevent noise escaping into the pcb because it couples into the pcb through the I/O traces of your IC.

No they don't. The order of connection is only important if the trace impedance is significant. At these frequencies and distances it isn't.

And if you really care about these tiny effects, the first thing you should do is get rid of the DIP parts, IC sockets, and leaded capacitors.

If it's easy and it works, then it is "right". What more do you hope to get ?

Ok here's my current layout. It's a 4 layer board wit the VCC and GND hidden. I've still got to route a few more tracks(they are the ultra thin yellow lines), but most of it's done. I used the remaining two tracks to route all the signals with a very occasionally dip into the VCC or GND layers when there wasn't a more feasible route.
What do people think?

It might introduce a few more vias but that is no biggie.

Why are you qualifying /RAM_SEL with Ø2?

You made some interesting component placement choices, which seem (to this untrained eye) to be causing a longer-than-necessary average trace length. Was this placement random, or was it affected by external constraints, like edge connector placement?

Mike