Hello everyone,

I have been working on putting a 65816 in my small board VIC 20. The schematic is matches the one on www.mainbyte.com. I have started with Ruud's 6502 ->65816 schematic, and it works. My next goal is to be able to latch A16..A23. First I tried the circuit in the data sheet, with no luck. After reading a lot of stuff about people learning the fine details of this tast, I though maybe I need to use of a delay circuit found in a number of locations on this forum, using inverters and an AND gate. Here's where I think I have a problem. I am using a Xilinx CPLD, (9500 series), to implement this delay circuit, using ISE 14.7. I am using the schematic entry method. When I compile the schematic and look at the equations produced, it looks like ISE is optimizing the circuit and removing the inverters that are there to create the delays. My VIC 20 is just running at 1 mhz and I am pulling the clock from fb11. The pullup resister is stretched across to the output of the inverter. I guess I am just trying to keep ISE from optimizing the circuit. I wouldn't think bus contention would be a problem, but it seems I read somewhere that it is. Any ideas would be welcome.

Welcome, A0CBM. What's the delay you're referring to -- the delay between what and what? -- and what problem is the delay intended to solve?

It'll be helpful if you post specific links to both circuits you mentioned -- Ruud's and the VIC20 -- thanks!

Jeff
ps- you may find it helpful to review the drawn-to-scale timing diagram in the topic Managing the 65816 multiplexed bus

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Latching the bank address from the data bus. From what I can find, there is a point of contention, when the bank address coming out of the 65816 may not be correct. Any time I mess with trying to separate the bank address from the data bus, the VIC 20 doesn't like it.

Welcome! Are you saying the machine doesn't work at all when you try to latch the bank bits, or that it works fine up until you try to make an access to a different bank?

You typically cannot implement asynchronous delays using gates in a CPLD/FPGA. The synthesizers will optimize out these constructions.

If you want to put in a asynchronous delay, you need to output the signal to an external pin (it may also be possible to use IO pads which are not bonded out) and loop the signal back into the CPLD/FPGA. The delay that you will get will be the sum of the output and input delay values given in the data sheet. Additional delay can be provided if you chain a couple of the pins together. It may also be possible to fine tune the delay by using the programmable slew rate and output drive controls available for most CPLD/FPGA outputs. Some of the more modern FPGA families provide user programmable input delay elements on many (if not all) inputs.

Hope this helps.

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Michael A.

Sorry, here's some of the sites I am referring to.

http://sbc.rictor.org/support/conv.html

http://www.mainbyte.com/vic20/manuals.html
the N-schematic at the bottom of the page.

http://www.baltissen.org/newhtm/02to816.htm

I have seen the to scale timing diagrams and have gone through all I could find on the forum regarding the 65C816. If I am correct in what I read, I don't need to latch the bank address for bank zero, which would be the actual VIC 20 system. It all seems to work fine until I try to latch that bank address.

I'm still a bit puzzled. You're trying to add delay between the Phi2 signal and the enable input of the address latch?

Also, is it your intention to use the extra address bits for extra memory space, or will your system stay within 64K (and merely exploit the improved '816 instruction set)?

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Yes, you have it Dr Jefyll, I am trying to add delay between PHI2 and the latch enable, and I do intend to add more memory above 0xFFFF.

So you've already gotten the '816 to work in the VIC20 -- is that right? -- and now you're moving to the next two steps:

• capturing the bank-address bits, and, when that's working,
• actually connecting those bits to the address-decoder circuits

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

That is correct.

Alright, so the '816 works in the VIC20. But when you try to capture the bank-address bits the VIC quits. And you haven't made connections to the address-decode circuit yet? There's something wrong if that's the case. If it was already working then merely capturing the bits (and sending them nowhere) shouldn't change anything. Can you supply more detail please?

[ps- woohoo, my 1,000th post! What a blabbermouth! ]

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I can try giving more details. I have tried using a 74HC573 as a latch. I am basically trying to implement the latch side of the circuit on pg 46 of the 65C816 data manual. I wouldn't think that would keep me from getting any display from my VIC 20, but it does.

Maybe I need to back up just a little more and just try hooking up the data bus to the latch inputs, nothing else, and see what it does. Then, if that works, hook up PHI2 to the latch enable.

This is the kind of detail I'm asking!

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

No, I have not made any connections to any decoding circuitry.

Hmm! Sounds a bit perplexing, in that case! If the outputs of the address latch are no-connect (as you've indicated) then delays and inverters won't help at this stage -- we need to fix the Mystery Problem first.

Troubleshooting involves a lot of careful observation. Maybe it's best to try moving step by step from the "without-latch VIC" that works to the "with-latch VIC" that doesn't. Break things down as much as possible.

Could you have accidentally created a short, maybe? Is the '573 in a socket? Does the VIC quit at the step when the 573 is inserted?

Excellent idea! At first I didn't notice you'd added this comment.

Cool project, BTW -- you're gonna have some fun with this when it's working! I'm envious

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html