I've asked about this previously and have set up a star ground and power using wire wrap. However, I'm now working on my first PCB based 65C02 design and want to be absolutely sure of how to implement this using a 4 layer board.

The PCB is going to be layered thus:

Top layer - signals
2nd layer - GND plane
3rd layer - Power/+5V plane
Bottom layer - signals

To make the power and GND planes into star one would I then divide those planes into sections something along the lines of this? The brown lines represent breaks in the copper.



[edit]

Here's an example of what I'm thinking.
Please ignore everything apart from the placement of the major ICs (the rest is not finalised and not routed properly (or not routed at all).
The dark-cyan background represents the GND plane and the red outlined tracks are being used to divide that plane into sections.

Is this correct? I think it is, but as getting a 4 layer board manufactured is going to be expensive I'd like to get this right .

My opinion is that such an arrangement has no value and may actually give rise to some issues.

The value of the inner layers as power and ground planes is that they are essentially uninterrupted. Hence the ESR of these layers is vanishingly small, which means that ground bounce and local Vcc fluctuations are largely eliminated. Also, the combination of the two layers acts like a sizable bypass capacitor, which can do quite a bit in keeping circuit noise to a minimum.

In my POC units, I did nothing to change the topology of the inner layers. Here's what the ground layer looks like in EPCB:


Other than where holes and via pass through, there are no interruptions. This circuit is dead quiet.


The above shows how I bring Vcc to devices. The theory is that any noise that is emitted out of the Vcc pin by the device is seen by the device's bypass capacitor before it gets to the inner power plane. The connection between device and capacitor is short and thick, which reduces the ESR to essentially zero. This practice is based upon recommendations by Dr. Howard Johnson, generally acknowledged to be the guru on this sort of stuff.

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So, is the message something like this:
- daisy-chaining all your devices in one long string is worst
- star connection is better
- thick wires are better than thin ones
- planes are best if you have the layers
- if you can only afford one plane, make it a ground plane
- whatever you do, have a bypass capacitor rather near each device's power pin and another bigger one where the power comes to the board.

Okey dokey. I thought that splitting them up would isolate high noise devices from each other to a degree, but I'll certainly be guided by you on this.

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One thing to note: Eagle does not seem to lend itself to connecting the VCC/VDD pin of an IC to the bypass cap which is connected to VCC - it just auto routes the IC pin to VCC. I have to detach the pin from VCC in the schematic and then manually connect the pin to the bypass cap in the layout editor. Anyone else getting this who use Eagle?

And if you can only afford two planes, make it two ground planes. It is important to keep impedance on ground connections low, but impedance in power supply lines isn't bad, as long as you have sufficient bypass caps near the chip. Even on four layer boards, I usually make 3 ground planes, and one power plane, although the power plane is mostly for convenience.

As long as the cap is close, it doesn't matter that the IC is also connected to VCC.

That's what I initially thought, but a lot of people are suggesting that it's best to route a short, thick track from the IC VDD pin to the bypass cap and have the bypass cap connected to the VDD layer.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

A perfect ground plane won't need any help. But on real boards, the ground planes aren't perfect. Two imperfect ones are better than one.

Currents follow path of least impedance. Offer multiple paths, and let the currents figure it out.

Is there a problem with running one track on top of another, non-interference?
I.e. on different layers.

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Gah routing buses is a nightmare! lol. I'm having to eat into the power plane a little to do it.

Two tracks running parallel will have some cross talk, both capacitive and inductive. The amount of cross talk depends on the distance (less distance = more cross talk), and length of the parallel section (longer = more), the material between, and the rise/fall times of the signal (shorter = more)

When two signals that change at the same time (e.g. two data lines from a bus), cross talk usually isn't a problem, because we're not interested in the signals when they are changing, only when they are stable.

In other cases, it could be a potential problem, for instance when running I2C signals right next to address bus, but it all depends on all the parameters above.

This is interesting, BDD. Did you refine your PCB from what is on your website?

At .... http://sbc.bcstechnology.net/images/sbc_pcb_org.jpeg ... there are traces to both sides of the caps, with the IC power pins connected to the planes.

Which way do you think is best? I have done a little reading and it seems everyone has their own opinion with this kind of 4 layer design. Somewhere I read suggests no traces at all were necessary, and the cap should simply be placed near to the IC. This does not seem right to me but then I am a complete amateur.

The frustrating thing for me, finishing off a very similar 4 layer design, is that KiCAD does not make these kinds of arrangements easy, since it wants to tie the lead (IC or cap) to the plane, directly.

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At the frequencies and distances we're talking about, there's not going to be any difference, so don't waste energy fighting the tools about this issue. I've made double sided boards that run at 100 MHz. Brad is doing 25+ MHz on breadboards. On a 4 layer board, with one empty ground plane, and caps near VCC pins, it's hard to make it fail.

In most cases with digital ICs, it would indeed be best to let the power or ground pin go directly to the plane, not first to a capacitor. There is a time for a version of the latter, but I won't go into that right now.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Cypress Semiconductor Corp., who makes very high speed static RAM, disagrees with you. Please see this post and read the attached white paper for their opinion, especially page 8 on the topic of power traces.


Yes. The PCB layout on my website is POC V1.0, the very first iteration (the website needs some updating). In POC V1.1, I rearranged power delivery to follow the advice in the above referenced white paper. Also, it wasn't necessary to tie the ground side of the bypass cap back to ground on the device it is decoupling. V1.1 was actually quieter than V1.0 because of these changes.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!