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banedon
 Post subject: Decoupling caps
PostPosted: Mon Nov 02, 2015 6:52 pm 
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Hi guys

Like all of us I use decoupling caps between VCC and GND pins on most ICs. However, when it comes to the DIP version of the 65C22 VIA this can be a challenge as the pins are about as far apart as they can possibly be. So... where would you put the decoupling cap if the top layer of the PCB is the ground plane? I.e. halfway between the two pins or right next to the VCC pin? Does the fact that you're attaching to an entire ground plane make any difference?
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Arlet
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 7:10 pm 
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I always put them next to the VCC pin to minimize impedance. If you use a ground plane, that side already has low impedance.
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GARTHWILSON
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 7:15 pm 
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Like Arlet says. If it's a true ground plane (pours don't really count), put the capacitor as close as possible to the Vcc pin, with connections to the Vcc pin and the ground plane as short as practical.

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What's an additional VIA among friends, anyhow?
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Arlet
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 7:38 pm 
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On two layer boards, I make ground pours on both sides, and connect them with plenty of vias, while trying to keep them as connected as possible. The idea is that the two sides combined will approximate a solid ground plane.

Here's a good example of a two layer board, partially running at 100 MHz: viewtopic.php?f=4&t=2453#p24570
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banedon
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 7:49 pm 
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Cheers guys. I'll amend my design.
Another thing (to hijack my own thread): Do you guys use the autorouter when you have tons of bus lines everywhere? I know most people tend to do it manually when they have small numbers of lines, but I'm find it a nightmare routing buses.
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Arlet
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 8:03 pm 
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I've never used an autorouter, except to try it out (in Eagle) and decide it was horrible.

What software are you using ?
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GARTHWILSON
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 8:46 pm 
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Autorouters may save time, but they lack the intelligence of a human. At my last place of work, we used OrCAD and tried its autorouter, and the results were, like Arlet says, horrible! I have laid out dozens of very dense boards for my work, and can say that to do a really good job, you have to be able to place and move parts while routing. You won't get the ideal design if you just sprinkle the parts in and route later. I don't use ratsnesting either.

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banedon
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 8:47 pm 
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Eagle. lol.

Ok, I'll try and do it by hand, but this may take some time...

[edit] Looking around, I've picked up the following advice:

- place ports and buttons/controls (HID) first
- place highest speed signal traces (buses), avoiding routing to different layers where you can
- place power traces
- place slower speed signal traces

Does this ring true with you guys? I'm asking as I'm planning to put together a simple 65C02 development system with 1x 65C02, 16KB RAM, 32KB ROM, 2xVIAs, 1xACIA, headers for buses.
This is going to have a fair amount of bus traces and I'm limited to a 4 layer board (I purchased the non-commercial version of Eagle(ouch!))
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Arlet
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 10:35 pm 
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Quote:
- place highest speed signal traces (buses), avoiding routing to different layers where you can

Actually, I often route a signal through different layers, even if there's room to keep it in a single layer. The reason is that I like to preserve the integrity of the ground planes. Having a small signal segment on one layer allows the ground to go around it, whereas a long trace on a single layer will often cut the ground plane in isolated segments. I especially don't like signals that snake around the board to reach a pin. I much prefer to insert a couple of vias and let it go straight.
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banedon
 Post subject: Re: Decoupling caps
PostPosted: Mon Nov 02, 2015 11:06 pm 
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Arlet wrote:
Quote:
- place highest speed signal traces (buses), avoiding routing to different layers where you can

Actually, I often route a signal through different layers, even if there's room to keep it in a single layer. The reason is that I like to preserve the integrity of the ground planes. Having a small signal segment on one layer allows the ground to go around it, whereas a long trace on a single layer will often cut the ground plane in isolated segments. I especially don't like signals that snake around the board to reach a pin. I much prefer to insert a couple of vias and let it go straight.

Don't you get a lot of resistance when going through multiple vias though?
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GARTHWILSON
 Post subject: Re: Decoupling caps
PostPosted: Tue Nov 03, 2015 12:26 am 
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banedon wrote:
Don't you get a lot of resistance when going through multiple vias though?

Not at all.

In multilayer layouts, you generally have each signal layer go a certain direction. If you have only two signal layers, they wold generally be -- and | . If something needs to go /, you will usually have to go over on one layer, take a via, and go up on the other. It might take multiple vias to get there, as you "sew" in the most difficult long connections. When you're mostly done, you can do some via minimization, not for reducing resistance, but sometimes for reducing drilling costs.

Things get extra interesting in surface-mount, because the pads don't have an automatic connection to all layers like we had in thru-hole, and you can't put vias in the pads. Vias take space.

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What's an additional VIA among friends, anyhow?
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Arlet
 Post subject: Re: Decoupling caps
PostPosted: Tue Nov 03, 2015 4:53 am 
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Quote:
Vias take space.

Yes, so it's worthwhile to check the design rules of your PCB manufacturer and see what the smallest via is that they can make (look for drill size and annular ring).

I do recommend surface mount components. Even for soldering novices, 0805 resistors and capacitors are no harder to work with than their through hole counterparts, and they do save space, especially routing space at the bottom.
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banedon
 Post subject: Re: Decoupling caps
PostPosted: Tue Nov 03, 2015 8:59 am 
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I've already put in SMD 0805 caps and resistors and the two reset ICs are also SMD.
Through-hole stuff is all the RAM, EPROM, CPU, VIAs and ACIA + all the pin headers (1x8 and 1x16 for bus access, 1x8 for signals access, 4x8 for VIA ports, 4x2 for CA/CB for VIAs, 4x2 for power connections (1 set for in, tyhe rest for aux out), 1x1 for clock in, 1x3 for clock input selection (between onboard oscillator and the clock pin). Lots of signals which go everywhere lol.
Oh, and the two tant 33uF caps are through-hole as well.
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GARTHWILSON
 Post subject: Re: Decoupling caps
PostPosted: Tue Nov 03, 2015 9:27 am 
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banedon wrote:
Through-hole stuff is all the RAM, EPROM, CPU, VIAs and ACIA + all the pin headers (1x8 and 1x16 for bus access, 1x8 for signals access, 4x8 for VIA ports, 4x2 for CA/CB for VIAs, 4x2 for power connections (1 set for in, the rest for aux out), 1x1 for clock in, 1x3 for clock input selection (between onboard oscillator and the clock pin).

Note that the IDCs that plug onto the pin headers come in fewer standard sizes: 2x5 (not 2x4), 2x7, 2x8, 2x10, 2x13, 2x17, 2x20, 2x25. (IDCs are the connectors you mount on ribbon cable by pressing them on with the bench vise or similar appropriate tool. They do not allow you to plug in offset by one or more pins.) I like to make the pin headers such that if you plug an IDC on backwards, you won't blow anything. You'll see this in my basic whole-computer design at the right end of the diagram at http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU . Keyed pin headers with ejector hooks are extra nice, but they take more board space.

This is getting a little more off-topic, but I don't recommend taking the processor's own buses off the board at the higher speeds. See the related page in the 6502 primer at http://wilsonminesco.com/6502primer/ExpBusIntrfc.html .

_________________
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What's an additional VIA among friends, anyhow?
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banedon
 Post subject: Re: Decoupling caps
PostPosted: Tue Nov 03, 2015 12:35 pm 
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Yep I totally agree with regard to not taking the buses off of the board. I have the headers there for fault finding only using my Bus Monitor project.
I'm not planning to use IDC connectors, but simple pin headers as I have now "mastered" the ability to create my own dupont pin headers. Saying that, IDC might not be a bad idea for the VIA connections offboard connectors.

BTW this project will be making use of your address decoding scheme as it's quite simple and fast (the schmitt trigger NAND gates) :).
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