Hi all

I've decided to create my own Eagle CAD library for 65xx parts, with a determination that the foot print/pads/etc are correct as I can rely safely have a proper PCB made.
Naturally, I've started with the 65C02S DIP... and surprisingly (as the data sheet is otherwise very good), the package dimensions appear to be missing. Most IC datasheets seem to have this information. As I don't want to guess this info, I might see if I can get it from an older NMOS datasheet, but if anyone has the proper/official measurements please let me know.

All 40-pin DIPs use the same dimensions. I just have one 40-pin DIP in my CAD, one 32-pin, a 28-pin for .300" wide and one for .600" wide, one 20-pin, one 18-pin, one 16-pin, one 14-pin, one 8-pin, and one 6-pin (for optoisolators).

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

As Garth said, DIPs are standardized by JEDEC, with strict requirements for overhang at the package ends—that overhang will not exceed 50 mils per end, except in very specific cases (for example, the EDIP package used in the Maxim DS1511Y RTC). If you measure the frame of a standard 40 pin DIP socket you will have what you need. Or, you can peruse the attached PDF. The socket in which you are interested is a 600 mil wide, 40 pin.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Great, many thanks .

Do people prefer using a PLCC symbol for a PLCC package, or do they stick with a DIP symbol despite using a PLCC package? Maybe this sounds obvious, but looking at the Eagle libraries it seems they are almost all DIP symbols no matter the actual package.

IMO the schematic symbol should be a logical representation of the part and not reflect the physical makeup at all. Group the connections by function, and ignore the physical layout, etc, etc. Then the schematic can be used to express what the circuit will do not how it will be wired.

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8 bit fun and games: https://www.aslak.net/

I don't want to start a discussion about the better pcb tool, but you should take a closer look to KiCad. As long as you don't have a license for the full version you're limited in the board size in Eagle (80x100mm for the free version). As well as for DipTrace, a pcb-tool I also worked with. In this tool you are limited in the number of Pads and Vias (300 in the free version). I could not have finished my own small 6 IC 65C02 system (MOUSE) with either Eagle or DipTrace, because the PCB is a default EuroBoard (160x100mm) in size and has 245 Pads and 100 Vias.
In KiCad you're not limited at all, because it is an OpenSource tool running in Linux, Windows and MacOs.

I've created a 65XX Library for KiCad some time ago: https://github.com/mkeller0815/65xx_Library
You will find also some handy chip label that can be printed and glued on top of a chip for easier wiring on the breadboard.

There are some things to learn for KiCad, because the workflow is a little bit different compared to other tools, but once you've got the trick and learned the keyboard shortcuts, it is really easy to work with.

Mario.

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How should I know what I think, until I hear what I've said.

The pin numbers will be different from DIP to PLCC though, and the pin numbers should show on the schematic.

I use CAD only for the PCB layout though, not the schematics, because of how much I dislike certain things that are problems (IMO) in all schematic CADs.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Eagle allows you to make a schematic symbol, and link it to a number of packages. While drawing the schematic, you pick a part + package, and it can automatically show the correct pin numbers in the schematic.

I agree with Aslak3 that the schematic symbol should represent the logical function, rather than physical shape. Also, when two parts are often used together, I like to match the schematic symbols (if it makes sense) so they can be connected using straight wires. I hate schematics where connecting wires are drawn in a tangled mess.

I'm not familiar with Eagle. What happens when the two packages don't have the same number of pins? (I did try an Eagle evaluation disc back when the internet hardly existed, and they said it absolutely, positively will not crash. Well, the demo crashed. )

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

In Eagle, every pin on the schematic must be matched to a physical pin on the package. But it is allowed for package pins to be unconnected, or for multiple package pins to be connected to the same schematic pin. In the case of unconnected package pins, it just omits them from the schematic. For multiple pins, it shows the first pin number, plus a '*N'.

I generally don't run "wires" from chip to chip. I use netlist symbols, as on the attached example, which helps keep down the clutter.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I do that too. I use wires for short and easy bits, and labels for the rest. I also don't usually run ground/vcc wires through the schematic, but rather use ground/vcc symbols (and strictly in their proper orientation: ground goes down, vcc goes up).

But, one of things I would do to your schematic is to modify the symbol for the MAX248 so that the pins for the charge pump caps would line up with the capacitors.

I tried that but the MAX-248 symbol became quite large. You can see how much space it already takes up, and that is on ANSI B size paper.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

For my schematics, I only use A4 paper in portrait format, so it's easy to print and read. However, I do make an effort to make the symbols as small as possible (while keeping them legible), and not try to cram too much on a sheet. I may have a sheet with just a single SDRAM chip plus decoupling caps, for instance.