Very good point about out-of-spec levels causing possible timing differences. A similar thing can happen with setup and hold times - a very late-arriving signal might get through, but the output be much delayed. Which is to say, even without considering metastability, the transit time of a latch can depend on meeting input timing.

I wired up a 74HC00 as an inverter and hooked the input up to a HP3325A function generator. I put channel A of my oscilloscope on the input, and channel B on the gate's output. Starting out with a 1 MHz square wave, I decreased the output amplitude until I got to the point where going any lower would result in dropouts on the output waveform. This occurred at approximately 2.4 volts (48% of VDD which was exactly 5 volts). I then increased the frequency of the signal generator to 5 MHz, and then to 10 MHz watching the output waveform for any issues. The main thing I noticed is that the gate took longer to switch on the rising clock than on the falling clock, which is consistent with Garth's earlier prediction. I've attached scope shots for the curious.

As far as I can tell, the HC04 I was using switched fine at 10 MHz (the 3325A won't generate square waves above 10 MHz so I didn't try to go higher for this quick experiment). This goes some way towards explaining why most people don't have trouble interfacing TTL to 5V CMOS logic at lower frequencies.

Taking this experiment further will involve a bit of additional circuitry. I could feed a higher frequency sine wave (3325A goes up to 20 MHz with sine wave output) into one of the HC00s other gates to square it up, then run that output through a 200-ohm pot and adjust it to 2.4 volts to drive the gate under test and probably get acceptable results.

In my POC unit, I have the ISSI SRAM, whose output follows the behavior of the Cypress SRAM, driving the MPU at 12.5 MHz, and have tested it at 15 MHz without the SCSI hardware present. So the MPU is seeing TTL level signals on the data bus, yet has no trouble reading the SRAM at 15 MHz. If it did, the POST memory sizing procedure would fail.


Even more interesting would be to try your experiment with 74ABT or 74AC hardware. Anyone attempting to run the 65C02 or 65C816 at "full throttle" is going to have to use at least 74AC logic in order to keep up.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

IMHO, using 74AC logic (I haven't used ABT logic, but from looking at the specs, I suspect it could be worse than the AC family) on a breadboard is a fool's errand. But let's see how the numbers stack up for a NAND gate along with my preferred logic family for high speed breadboard use (typical times listed):

74AC00: T(PLH) = 6 nS, T(PHL) = 4.5 nS
74ABT00: T(PLH) = 2.5 nS, T(PHL) = 2.0 nS
74AHC00: T(PLH) = 5.5 nS, T(PHL) = 5.5 nS

While the ABT is the clear winner here in terms of speed, the AHC devices are about as fast as the AC logic but their switching transients are far better. I don't know much about the ABT logic family offhand, so all I can say is that if they are not slew rate limited, they are going to cause even worse ground transients than the AC logic which is already horrible. Also, ground bounce problems caused by these fast devices will be exacerbated in circuits that use TTL logic levels.

Here is an excerpt from TI's literature on the AHC family:


This is why I'm a big fan of these devices, especially when working with breadboards or PC boards without dedicated ground planes.

I will try the experiment again a bit later tonight replacing the gate with a 74AHC to see if the behavior is substantially different. I may also try cranking up the switching frequency to 20 MHz as well.

I went ahead and repeated my previous experiment with a 74AHC00 gate and a 74AC00 gate.

I discovered that V(ih) for the 74AHC00 gate was higher than it was for the 74HC00 -- it needed about 2.7 volts. The 74AC00 was slightly better at 2.6 volts. The waveforms for both signals look quite similar. One small but possibly significant difference is that you can see what appears to be some gate charge effects showing up on the input waveform of the AC logic but not the AHC logic. Both the rising edge and falling edge of the input on the AC waveform show this effect, but it is not visible on the AHC logic. This is consistent with the AC using larger FETs in order to switch higher currents.

Here are the scope shots for the AHC logic:

(couldn't fit all of the images in the previous posting, so here are the AC scope shots referenced from the above post):

No disagreement there. Switching transients on a breadboard would be brutal and the ground voltage would look like a basketball being dribbled down-court. Even wire-wrap would be problematic. I build my units on a four-layer PCB with internal ground and power planes to try to keep a lid on noise. So far, so good.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!