As a prelude to testing a PIC-based UART replacement, I find myself in need of a simple 6502-based computer for testing and prototyping purposes. To that end, I've put together a simple design and started building it.
The goals of this system are as follows:
- Breadboardable
- Little (preferably no) soldering required
- No EPROMs
- No DRAMs
The only potentially interesting thing about this system is the ROM Emulator. It should probably come as no surprise that I'm using another PIC microcontroller to create it. The PIC holds the 65C02 in reset and causes it to release (tri-state) the address and data lines by setting BE low. Then it loads the contents of the upper 8K of CY7C199 SRAM with a user-specified program. Once that's done (hopefully not more than a couple of seconds), the PIC releases the address and data lines it was controlling, enables the 65C02 BE and releases it from reset. Here are the preliminary schematics for the hardware buffs. When it gets closer to final form, I'll redraw it as several sheets in AD for readability and archival purposes.
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(sheet 2):
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And here is the breadboard work in progress for those who prefer eye candy:
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The only testing I've done so far is to wire up the data lines to return NOP and then check the address lines for expected operation.
Here is the memory map I have in mind:
0000-7FFF: CY7C199 SRAM #1
8000-9FFF: CY7C199 SRAM #2
A000-BFFF: CY7C199 SRAM #2
C000-DFFF: HW PERIPHERALS
E000-FFFF: CY7C199 SRAM #2 (read only)
The address decoding logic is straightforward. The only thing special it needs to do is to disallow writes to the last 8K of the SRAM by the 6502, but allow it by the PIC. I was originally accomplishing this by putting a 74HC245 tri-state buffer on the decoder logic output to the WEn lines on the CY7C199, but it occurs to me that I may be able to slightly simplify the design using another 74HC139 and a leftover gate instead. Need to check the gate delays though to make sure it's not worse. There's probably other simplifications to be made that I haven't found yet as well.
Initially, I'll be clocking the 65C02 at 1.8MHz in order to test it with the "real" UARTS I have on hand (68B50s). Once the system is up and running correctly, I'll replace the 68B50 with my PIC UART and begin development and testing of that subsystem. Eventually I will turn up the clock speed further to see how close to 14 MHz I can get.
A larger PIC (I don't have anything in DIP form larger than 28-pins at the moment) could control a display, and interface to a FAT filesystem stored on a microSD card. In fact, there is nothing stopping the PIC from programming all 56K (64K-8K) of SRAM either so it could serve not only a role in ROM emulation, but also as a program loader in much the same way flash is used with FPGAs.
[10/11/15 - Updated schematic and board image]