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 Post subject: Re: Beholder project
PostPosted: Sat Oct 03, 2015 12:11 am 
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beholder, fine-grained address decoding takes more logic and more propagation delays. For slow systems, you can stop wasting and save less than a quarter of the memory map, but turning up the speed requires the simpler logic, and the truth is that 64K of assembly language is an awful lot for a single hobbyist to fill. My first big commercial software project (big considering I was the only one working on it) was in 65c02 assembly language and IIRC it took about 24K. The list file printed out to about an inch of paper. I learned later how to do the same things more efficiently anyway. If you need more memory, it will most likely be for either a lot of data, or an inefficient C compiler. (See my C-versus-assembly example of an empty count-to-100 loop just over half way down the page in my article on the relevance of assembly language today, at http://wilsonminesco.com/AssyDefense/ .

On your code there, note that you can use [code] and [/code] around it to make it come out monospaced (as all source code should be) and with the spaces all there, instead of it reducing six spaces for example down to one. It's like the <pre>...</pre> (preformated) tags in html. (I did another trick here to keep [code] and [/code] from doing their job.)

Also, the registers should be specified by name to make them much more intelligible to humans, to make you more productive, and to get fewer bugs, and to make the code more maintainable. Then the assembler converts the names to numbers, according to the EQUates you put earlier in the code. So before referring to the registers in the I/O ICs, you'll have something like:
Code:
VIA1:       EQU  $6000       ; Base address of first 6522 VIA on SBC.
VIA1PB:     EQU  VIA1 +  0   ; Addresses of various registers in 6522.  First, Port B.
VIA1PA:     EQU  VIA1 +  1   ; Port A
VIA1DDRB:   EQU  VIA1 +  2   ; Data Direction Register for Port B
VIA1DDRA:   EQU  VIA1 +  3   ; Data Direction Register for Port A
VIA1T1CL:   EQU  VIA1 +  4   ; Timer 1 Counter Low  byte
VIA1T1CH:   EQU  VIA1 +  5   ; Timer 1 Counter High byte
VIA1T1LL:   EQU  VIA1 +  6   ; Timer 1 Latch   Low  byte
VIA1T1LH:   EQU  VIA1 +  7   ; Timer 1 Latch   High byte
VIA1T2CL:   EQU  VIA1 +  8   ; Timer 2 Counter Low  byte
VIA1T2CH:   EQU  VIA1 +  9   ; Timer 2 Counter High byte
VIA1SR:     EQU  VIA1 + $A   ; Shift Register
VIA1ACR:    EQU  VIA1 + $B   ; Auxixiary  Control Register
VIA1PCR:    EQU  VIA1 + $C   ; Peripheral Control Register
VIA1IFR:    EQU  VIA1 + $D   ; Interrupt  Flag  Register
VIA1IER:    EQU  VIA1 + $E   ; Interrupt Enable Register
VIA1PANOHS: EQU  VIA1 + $F   ; Port A, but with No Handshaking

VIA2:       EQU  $5000       ; Base address of second 6522 VIA on SBC.
VIA2PB:     EQU  VIA2 +  0   ; Addresses of various registers in 6522.  First, Port B.
VIA2PA:     EQU  VIA2 +  1   ; Port A
VIA2DDRB:   EQU  VIA2 +  2   ; Data Direction Register for Port B
VIA2DDRA:   EQU  VIA2 +  3   ; Data Direction Register for Port A
    -----etc.------

When writing on the forum, the box we have to write in does not show the vertical alignment right, so you'll probably want to copy out of a text editor.

If you only have one VIA, you can drop the VIA1, VIA2, etc. and just use the register names, then your piece of code above will be something like:
Code:
        LDA  #$FF
        STA  DDRB   ; Make both PA and
        STA  DDRA   ; PB to be all outputs.
        LDA  $00    ; Load the value (3) from ZP RAM
        STA  PB     ; and cause both PA and
        STA  PA     ; PB to reflect that value.

These and many more basic programming tips are in the programming tips page of the 6502 primer.

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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 Post subject: Re: Beholder project
PostPosted: Sat Oct 03, 2015 7:09 am 
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Hi beholder,

have a look at the following thread http://forum.6502.org/viewtopic.php?f=4&t=3374. Here I use the same ATmega328P as on Arduinos. The problem with pipeing instructions to the 6502 without knowing what the status of the 6502 processor is, you need to "know" or "predict" what the 6502 expects. As already stated you should use SYNC to know when the 6502 fetches an instruction. Then you can pipe all further bytes that belong to an instruction, which always are the subsequent reads. Then the 6502 either reads data, adds a dummy cycle or writes data. If you also add RW to the Arduino you could even tell what he does. However the type of instructions you can use is very limited as branches depend on the internal status and you don't know that (you could guess that a branch is taken, when the cycle after reading the branch instruction and offset is not an instruction fetch cycle that is SYNC is not asserted, of course the Arduino must keep some track of the PC to correctly provide the next instruction). So I think you should have a look at the thread I linked. Here the "Arduino" MCU pipes a very primitive program where each cycle can be predicted used to download a program to RAM. In my case I load the program to the upper RAM region that is then write-protected, activate the mapping so this RAM region acts as ROM and reset the 6502 again to really start the ROM. However you could also just load a program using this instruction sequence and then pipe a JMP to the start of the program and then let the 6502 execute from the program you just loaded to the RAM. That's what the SID player mentioned in the thread does.

As for the VIA symbols. I usually only define one set of offset symbols and then define base symbols for each instance
Code:
DDRB        EQU 2

VIA1         EQU $C090
VIA2         EQU $C0A0


STA         VIA1+DDRB





Then you can also use the offset symbols to be loaded into the index registers to use indexed instructions (LDX #DDRB). The advantage is that when you change the hardware you only need to change one symbol and the offset symbols do not depend on the number if VIAs you have.

Cheers

Peter


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 Post subject: Re: Beholder project
PostPosted: Sat Oct 03, 2015 7:24 am 
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beholder wrote:
Have a quick question regarding the 6522
Since you only need 1 byte to access the VIA chip, isn't it wasting space in the address bus?
Mine is mapped from $4000 to $7FFF, but it only uses $6000 to $600F.

As Garth noted, fine-grained address decoding incurs performance and complexity penalties. For that reason, many of the eight bit home computers of bygone days would assign an entire page of addresses to a single device, even though that device might have had very few registers. For example, the CSG8563 video display controller (VDC) in the Commodore 128 occupied space from $0D600 to $0D6FF, but only had two registers. It simply wasn't "economical" in terms of silicon to decode the VDC to a smaller space, as the required logic would have been considerable and quite slow.

When I designed my POC unit, I placed the I/O block at $00D000, with it decoded into one page segments. The real-time clock is at $00D000, the DUART is at $00D100, the SCSI host adapter at $00D200, and so forth. That was the best compromise between economizing on addresses and not introducing too many gate delays into the system. I used the familiar 74AC138 decoder for selecting I/O devices and have no more than two gate delays between the decoder and the address bus. Timing is fast enough to support 15 MHz operation, although not all of the I/O hardware can handle that speed.

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 Post subject: Re: Beholder project
PostPosted: Sat Oct 03, 2015 7:33 am 
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cbscpe wrote:
As for the VIA symbols. I usually only define one set of offset symbols and then define base symbols for each instance
Code:
DDRB        EQU 2

VIA1         EQU $C090
VIA2         EQU $C0A0


STA         VIA1+DDRB


Then you can also use the offset symbols to be loaded into the index registers to use indexed instructions (LDX #DDRB). The advantage is that when you change the hardware you only need to change one symbol and the offset symbols do not depend on the number if VIAs you have.

That's how I define much of the I/O in my POC unit. For example, the real-time clock architecture is coded as follows:

Code:
;================================================================================
;
;DALLAS DS1511 REAL-TIME CLOCK REGISTER DEFINITIONS
;
nr_rtc   =32                   ;total registers ($14-$1F reserved)
;
;
;   register offsets...
;
wr_sect  =$00                  ;TOD seconds ($00-$59 BCD)
wr_mint  =$01                  ;TOD minutes ($00-$59 BCD)
wr_hrst  =$02                  ;TOD hour ($00-$23 BCD)
wr_dowt  =$03                  ;day of week ($01-$07 BCD)
wr_datt  =$04                  ;date ($01-$31 BCD)
wr_mon   =$05                  ;month & control...
;
;   xxxxxxxx
;   ||||||||
;   |||+++++———> month ($01-$12 BCD)
;   ||+————————> 1: enable 32 Khz at SQW when on battery
;   |+—————————> 0: enable 32 KHz at SQW when on Vcc
;   +——————————> 0: enable oscillator
;
wr_yrlo  =$06                  ;year LSB ($00-$99 BCD)
wr_yrhi  =$07                  ;year MSB ($00-$39 BCD)
wr_seca  =$08                  ;alarm seconds & IRQ control...
;
;   xxxxxxxx
;   ||||||||
;   |+++++++———> alarm seconds ($00-$59 BCD)
;   +——————————> 1: IRQ once per second
;
wr_mina  =$09                  ;alarm minutes & IRQ control...
;
;   xxxxxxxx
;   ||||||||
;   |+++++++———> alarm minutes ($00-$59 BCD)
;   +——————————> 1: IRQ when TOD secs = alarm secs
;
wr_hrsa  =$0a                  ;alarm hour & IRQ control...
;
;   x0xxxxxx
;   | ||||||
;   | ++++++———> alarm hour ($00-$23 BCD)
;   +——————————> 1: IRQ when TOD secs & mins = alarm secs & mins
;
wr_dowa  =$0b                  ;alarm date/day & IRQ control...
;
;   xxxxxxxx
;   ||||||||
;   ||++++++———> alarm day ($01-$07 BCD) or date ($01-$31 BCD)
;   |+—————————> 0: alarm date set
;   |            1: alarm day set
;   +——————————> 0: IRQ when TOD & day/date = alarm TOD & day/date
;                1: IRQ when TOD = alarm time
;
wr_wdms  =$0c                  ;watchdog millisecs*10 ($00-$99 BCD)
wr_wds   =$0d                  ;watchdog seconds ($00-$99 BCD)
wr_cra   =$0e                  ;control register A...
;
;   xxxxxxxx
;   ||||||||
;   |||||||+———> 1: IRQ pending (read only)
;   ||||||+————> 1: IRQ = watchdog timer
;   |||||+—————> 1: IRQ = kickstart (read only)
;   ||||+——————> 1: IRQ = TOD alarm
;   |||+———————> 0: PWR pin = active low
;   |||          1: PWR pin = high-Z
;   ||+————————> 0: PWR pin = high-Z wo/Vcc present
;   ||           1: PWR pin = active low wo/Vcc present
;   |+—————————> 1: aux external battery low (read only)
;   +——————————> 1: external battery low (read only)
;
wr_crb   =$0f                  ;control register B...
;
;   x0xxxxxx
;   | ||||||
;   | |||||+———> 0: watchdog generates IRQ
;   | |||||      1: watchdog generates reset
;   | ||||+————> 1: watchdog IRQ/reset enabled
;   | |||+—————> 1: kickstart IRQ enabled
;   | ||+——————> 1: TOD alarm IRQ enabled
;   | |+———————> 1: TOD alarm wakeup enabled
;   | +————————> 1: NVRAM address autoincrement enabled
;   +——————————> 0: TOD & date register update disabled
;                1: TOD & date register update enabled
;
wr_nvra  =$10                  ;NVRAM address port ($00-$FF)
wr_rsva  =$11                  ;reserved
wr_rsvb  =$12                  ;reserved
wr_nvrd  =$13                  ;NVRAM data port

The only absolute address assigned to the RTC is its base address in the memory map ($00D000). Everything else is done using register offsets.

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 Post subject: Re: Beholder project
PostPosted: Sat Oct 03, 2015 8:21 am 
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It's just for simplicity of decode: the laziest practical decode will put a single device across 16k of memory, and as you decrease the footprint you need to add logic. Most designs will map a VIA into a slightly larger space, like 32 or 64 addresses, just to save a little on the decoding. It's fine, if there's nothing else to place in the address space. In the old days, you could hardly fill 64k - the Apple 1 used 8 chips for 4k of RAM and two chips for just 256 bytes of ROM. These days, a single RAM chip can cover 64k many times over.

In practice there's not a lot of difference between a machine with 60k of usable RAM and one with 63.5k of usable RAM - unless you have a large application which makes assumptions. So the last bit of decoding is still not necessary in most cases.


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 Post subject: Re: Beholder project
PostPosted: Sat Oct 03, 2015 11:41 pm 
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Quote:
It's just for simplicity of decode: the laziest practical decode will put a single device across 16k of memory, and as you decrease the footprint you need to add logic. Most designs will map a VIA into a slightly larger space, like 32 or 64 addresses, just to save a little on the decoding. It's fine, if there's nothing else to place in the address space

One place where decoding right down to the byte occurs is when placing things into the zero page area of memory. It's important not to waste zero page addresses, but sometimes I/O is placed in zero page.

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 Post subject: Re: Beholder project
PostPosted: Wed Oct 07, 2015 2:32 am 
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Posts: 63
Hi everyone!

Thanks for all the great feedback and explanations!
I've been reading and re-reading all the responses to absorb all the new information and understand :)
Now I do understand why keeping a simple address mapping schematic will keep you from dealing with propagation delays.
I did read the primer on propagation delay, but only realized it was the reason the VIA was mapped that way after reading your posts.
So if I add more logic ic to map the 64k to various ICs it will slow down and possibly not work, right?
Then getting the 6502 at 10MHz will require a simple schematic, correct?

Yes, with the arduino Im predicting all the outcomes and have simple code to test it.
So far reading the R/W, A15 and sync have been super helpful, but I want to get my ROM on the board soon.
I should be programming my eeprom very soon :)
Just waiting for my order of 74HC595 so I can make the meeprom programmer.

Thanks for all the code writing feedback!
Right now Im not using a compiler, just writing it directly on arduino.
I did created a few variable to have the VIA address kinda like the examples you gave me.

So far got RAM and VIA working with the 6502.
I've added a AY-3-8910 and spent a good time reading the datasheet and this nice arduino example:
http://playground.arduino.cc/Main/AY38910

I ended up using the VIA to drive the AY chip and it worked!
I can see it outputting a signal, but need to make an amplifier circuit to hear it.
Im waiting for an LM386 that I just ordered.

Today I found this schematic on 6502.org and it's exactly how im controlling my AY :)
http://kaput.homeunix.org/~thrashbarg/ay-3-8912.png

Looking at this AY-3-8910 datasheet there is an example of hooking it up with a 6800 using a VIA the same way:
http://dev-docs.atariforge.org/files/AY ... b-1979.pdf

I guess using the VIA to control the AY-3-8910 is the way to go right?
Thanks!


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 Post subject: Re: Beholder project
PostPosted: Wed Oct 07, 2015 8:10 pm 
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I have used regular PC speakers with an AY with good results, if you just want to see erm hear it working with a minimum of work.

I cover the AY in one of my blog posts:

http://aslak3.blogspot.co.uk/2013/11/so ... om-cf.html

It's using a 6809 but the CPU busses are rather similar. Basically you can attach the AY directly to the CPU bus you just need some extra, slightly weird, glue. It also makes addressing the part interesting from the code. It's certainly preferrable to using a VIA though.

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 Post subject: Re: Beholder project
PostPosted: Thu Oct 08, 2015 2:50 am 
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Hi Aslak3.

Wow! It worked :D
I can finally hear the notes!
Thanks, did not know I could just connect to the speakers.
I was about to make an amp circuit.

Will look into having it connected to the cpu instead of the VIA
Thanks


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 Post subject: Re: Beholder project
PostPosted: Thu Oct 08, 2015 4:51 am 
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Joined: Wed Sep 02, 2015 7:28 pm
Posts: 63
Here's my latest video update on my 6502 project:
https://www.youtube.com/watch?v=vSBBjI9mMW0

Got the AY-3-8910 working !
You can hear the notes :)

Next goals:

- program my EEPROM
- have the sound chip play a song
- have VIA read inputs

Thank you all for the feedback and help. Wouldn't be this far without it!
Cheers


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