I know the 6502, when writing, keeps the data valid on the data bus for about 30ns after PHI2 drops, to ensure the data is latched correctly. Say PHI2 and R/W are fed into a series of logic gates, the output of which is connected to /WE on a memory chip, to ensure writing only occurs when PHI2 is high and R/W is low. Wouldn't propagation delay cause the falling edge of PHI2 to not be detected at /WE until after the data hold time? The propagation delay of a logic gate can be up to 18ns, so why does this scheme work?

Bus capacitance will hold the data longer than you might think, just because the output gets tri-stated and there's typically nothing else driving it for awhile.

WE\ typically gets connected directly to the R/W\ line with no other logic in between, and then phase 2 is brought into the memory's select logic. Using separate RD\ and WR\ is typical of other systems, not the 65 family. On the 6522 and 6551 peripheral ICs with a phase-2 input, phase 2 must not be brought into the select or R/W\ inputs, or the part won't work. You can have RAM, ROM, and up to ten I/O ICs in a 6502 system using nothing but a 74HC00 quad NAND for glue logic. It makes it very simple.

I'm not sure how you're arranging this to occur, generically. I'm assuming you're referring to 6522s specifically when you say I/O ICs?

I ask because the only way I can see that happening is to let A15 drive all the ICs _CS2, then let specific address lines drive the CS1 inputs (A14 for VIA 1, A13 for VIA 2, A12 for VIA 3, etc). This creates rather interesting situations where you can write to multiple VIAs in a single CPU instruction, but equally and most dangerously, you can also attempt to *read* from multiple VIAs too. So while it's doable, it's dangerous for bus contention issues.

> I'm assuming you're referring to 6522s specifically when you say I/O ICs?

I'm referring to any of the I/O ICs that have both a positive-logic select and a negative-logic select which must both be true to select the part, and that have a separate phase-2 input. That would include the 6522 and 6551, plus several 65xx parts that are not in current production.

> rather interesting situations where you can write to multiple VIAs in a
> single CPU instruction,

Yes, you can write to more than one at a time if you want to, but nothing says you have to. It might be useful if you want to do identical setups on more than one ACIA at a time for example, although I've never done that. As far as reading them, reasonable care will avoid the bus contention. I just set up the address constants at the beginning of the program, and it has never been a problem in all the years I've been in this racket.

http://www.6502.org/users/garth/project ... chematic=2 shows my workbench computer's address decoding. The inverters could be replaced with other sections of the quad NAND if that was all I had. (Actually I did do it that way on another computer.) The inverter "pointing" to the left was for something I never implemented. Now I don't even remember what it was. IOW, the whole thing could be done with three sections of a quad NAND 74xx00.

I don't recall saying that you HAD to.



Aren't rackets illegal? ;D

By how long does bus capacitance typically "extend" the hold time? It would help me understand Daryl Rictor's SBC-2 v2.5 schematic, in which the 65C02, with a data hold time of only 10ns, can still write to the 62256 SRAM even though PHI2's falling edge is not detected at /WE until as much as 15ns after (due to the NAND gate).

I also notice that in his schematic, PHI2 is ignored for reads. Is the data bus guaranteed to be high impedance by the time R/W goes high after a write?

(Sorry about the simple questions, I don't understand timing very well yet.)

> By how long does bus capacitance typically "extend" the hold time?

Let's say the leakage of everything combined on a given data bit net was 100K ohms to Vcc (which in this case is worse than leakage to ground or to both Vcc and ground) and the capacitance were 40pF. That time constant is 4µs. Even .1TC (approximately the time in this case to go from .3V to .8V) is 400ns; but your leakage is probably less (ie, higher resistance), so I don't think you have a thing to worry about there. This low level of leakage assumes MOS loads and no bipolar logic loads, since the bipolar (like 74LSxx) take DC input current, unlike the MOS (like 74HCxx, 74HCTxx, 74ACxx, 74ACTxx, etc. and all modern memories).


> I also notice that in his schematic, PHI2 is ignored for reads. Is the
> data bus guaranteed to be high impedance by the time R/W goes high
> after a write?

No, although the short amount of time (a few ns) may not be enough to get much current going through the parasitic inductances in the circuit. You might however be able to make a small reduction in supply current or in the generated electrical noise by taking care of that issue.

It's good that you're looking at the timing diagrams and spec.s in detail. A lot of people get themselves in trouble by ignoring them.