GARTHWILSON wrote:
The many wait states that would be needed in any I/O intensive situation sound like quite a performance killer.
Depends how you do it, I naturally also thought that a select would cause the AVR to enter a interrupt routine. But this is not necessarily so. You could also poll the CS signal. Then you need to read the relevant address bits and RW status and jump to the appropriate routine, using a 256-instructionword aligned jump table would use only very few cycles
Code:
ldi zh, high(iotable)
cbi PIND, DONE ; Prepare for next IO
sbic PIND, CS
rjmp housekeeping ; If you want something be done, else it's just jumping to the cbi
in zl, PINA ; Assume we read A0..A6 and RW with this
ijmp
align 8
iotable:
rjmp readioreg
.
.
.
rjmp writeioreg
readioreg:
thats only 7 cycles. Then you do your task, that is transfer the byte from/to the register to a buffer (e.g. a 74HCT652 type interface between the 65C02 and the AVR). In other words a non-disturbed IO read/write
would take about 20 AVR cycles. Michael's 3-chip design uses 16 AVR cycles to do everything a 65C02 expects to happen in one PHI2 cycle. When you think about the number of IO access a IO routine does in relation to the code it must execute (LDA ioaddress and a Bxx LOOP) the relative performance degradation is not that that important. Imagine that a 20MHz AVR would only throttle systems running at more than 1MHz and only during AVR IO cycles. In a typical application only a few cycles. If you are doing some real-time stuff and require a lot of IO cycles due to your system requirements, then this is definitively not the solution. So whether the performance penalty is relevant or not depends a lot on your application.
GARTHWILSON wrote:
BTW, RDY is a positive-logic signal. Pulling it down constitutes negating it, meaning "No, I'm not ready to move on. I need more time." High (asserting it) means, "Yes. Ready. Go."
Yes of course, I got it all messed up. Thanks for clarifying.
Dr Jefyll wrote:
I modified one of my other wait-state diagrams, Peter -- see what you think of this (below).
Jeff, thanks a lot, looks promising. Just that with J=H and /K=L the ff will toggle, so I will probably add another flip-flop between DONE and J to limit the DONE=High time to one PHI2 cycle. But the good thing about your approach is that each state change is synchronous to PHI2 and that is what is important in such a circuit.
BigDumbDinosaur wrote:
The reason devices such as UARTs exist is they do very efficiently in hardware what a microcontroller less efficiently and more slowly in software.
Contrary to the subject of this post (which was not started by me btw.), I'm primarily interested in the following IO features of the AVR: I2C, SPI, ADC, Timers with PWM outputs. The USART is interesting because of it's synchronous mode. So you can connect a PS/2 keyboard and a Mouse and the USART does all the frame checks (start-bit, parity-bit, stop-bit). Also using the USART of the AVR we do not do anything in software related to the RS-232 protocol. The only difference in efficiency comes from the fact that a read/write to a register is slower than that of your preferred UARTs.
BigDumbDinosaur wrote:
The only thing I'd add to that circuit is a small Schottky diode in between the flop's Q output and the MPU's RDY pin, as RDY is bi-directional.
Yes of course and also the pull-up should not be to weak.