1. The Commodore 6502 datasheet states that the address bus and data bus are "capable of driving one standard TTL load and 130pf." Could someone explain exactly what this means, in relation to the number of external components that may be attached to the buses?

2. The STMicroelectronics 28C64 datasheet states a minimum "Time Delay to Read" of 1us and a minimum "Time Delay to Write" of 10ms. Does this mean no reads or writes should be attempted until these times have passed after power is first applied?

> The Commodore 6502 datasheet states that the address bus and data
> bus are "capable of driving one standard TTL load and 130pf." Could
> someone explain exactly what this means, in relation to the number of
> external components that may be attached to the buses?

Hopefully someone who's more of a computer-parts historian will fill in or correct a few details here, but since no one else has jumped in so far, I'll give it a try. It might be more than you bargained for, but hopefully will answer the question in a round-about way.

In the early days of commodity logic ICs (starting in the 1960's), the 7400 line (and 5400 for military) was standard, and people built all kinds of circuits with these building blocks. They were TTL, which stood for "transistor-transistor logic," as opposed to DTL (diode-transistor logic) or RTL (resistor-transistor logic) or any other combinations I might be forgetting. I've had surplus circuit boards (single- or double-sided, as this was before multilayer) with scores of these ICs and no processor on them. There was no programmable logic yet to cut the parts count down. Internally these TTL logic gates used bipolar transistors (mostly NPN, since they were generally faster than PNP). Bipolars, unlike MOS, require base current to turn them on. This led to fan-out limitations, since one output could only drive so many inputs' current requirment. 7400 logic consumed a lot of power, even when not switching. Low-power TTL (the 74Lxx family) consumed a lot less power, but was also slower and could not drive as much of a load. When low-power Schottky (74LSxx) came out, the speed penalty was gone, although LS still couldn't drive as much as plain TTL could.

A TTL DC input current load is generally regarded to be 40µA for a valid logic-high level, and 1.6mA for a valid logic-low level. Actual current needed for a particular TTL input may be lower.

Later, CMOS (complementary metal-oxide semiconductor) logic used MOSFETs (metal-oxide semiconductor field-effect transistors) instead of bipolar transistors. One of the advantages of MOSFETs is that the current through them was controlled only by the electric field set up by the voltage on the transistor's gate, instead of by a constant current flowing like a bipolar transistor required at its base. There was still some input capacitance; but once that was charged up after the input logic level changed, the gate current was essentially zero. This not only helped reduce the power consumption, but improved the fan-out rate. Now the fan-out was only limited by speed, since more inputs connected to an output would present more capacitance to charge up, requiring more time to charge.

The first popular CMOS logic family was the 4000 series. This family could handle a much wider operating voltage range (about 2-15V), but was very slow compared to TTL. 74HCxx (high-speed CMOS) and 74HCTxx (with with 100%-compatible TTL-logic-level input thresholds) are not made to take more than 6V, but are approximately the speed of LSTTL-- usually a hair faster, and sometimes a little slower. There really is virtually no reason left to use any non-CMOS logic today, so the capacitance spec is the main one of the two you mention that you need to pay attention to. Memory and I/O ICs virtually always have MOS inputs too, which again take no appreciable current other than to charge their capacitances when the logic level changes.

The datasheet gives a maximum amount of capacitance, in pF (picofarads) that can be driven without slipping on the guaranteed timing specifications. A CMOS logic input generally gives about 5pF of capacitive loading. The traces (or wire-wrap wires) on the circuit board will also give a small amount. These need to be added up for any given net that a particular output drives. As you can see, 130pF divided by 5pF is 26 loads the output could drive while meeting the speed specifications, not taking the minor circuit board and IC-socket capacitances into account. Even if those mean cutting it down to 15, that's probably more than you planned to put on there. You could buffer the processor's buses, but buffering also adds delays; so if you're really that close to the raggedy edge, you may need to slow the clock speed down or rethink the design.

http://www.6502.org/forum/viewtopic.php ... ght=pullup has more on logic delays and compatibilities, along with URLs to lots of ap. notes.


> 2. The STMicroelectronics 28C64 datasheet states a minimum "Time
> Delay to Read" of 1us and a minimum "Time Delay to Write" of 10ms.
> Does this mean no reads or writes should be attempted until these
> times have passed after power is first applied?

The read time is the maximum amount of time it should take from the time the address and selects are valid to the time the data output is valid and stable. If it's really 1µs, that's extremely slow, and won't even let your 6502 processor run at 1MHz. Slow EPROMs are 450ns, and most now are four times that fast, with the fastest EPROMs at about 35ns or 55ns. Getting under 10ns is pretty inexpensive now with SRAM.

The write time for an EEPROM will always be much longer than the read time. EEPROMs are not made to be constantly written to by running programs in the target computer, and would be worn out right away. For the running program, you'll be constantly storing to RAM, since its write time is similar to its read time and it won't wear out from writing to it gazillions of times.

Thanks Garth.

The 28C64 is actually relatively fast, with an "Address Valid to Output Valid" time of 250ns, and a "Write Cycle Time" of 1ms. The 1us minimum "Time Delay to Read" and 10ms minimum "Time Delay to Write" specs were stated in a "Power-up Timing" table, which I assume refers only to when power is first applied. I plan to use a DS1813 EconoReset in my 6502 project anyway, so I suppose these delays wouldn't matter much.