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My problem with that approach is that I wouldn't know where to begin with the proper timing specification for that. Do you have experience with this ?
Yes, specifying timing may be the problem.
I had the FISA64 cache setup this way for a while and it seemed to work, but I switched it to using the negative clock edge instead. It may have been giving me timing error messages which I ignored.
I didn't use an explicit timing spec in a constraints file as the clocks are all related to (synchronous to) a master clock. The tools check for proper timing automagically.
It's the same idea as using the negative edge of the clock to clock the BRAM. Using the negative edge of the clock is similar to using a 2x clock. It gives 1/2 the time to access the BRAM.
It does mean you have to generate another clock and pass the clock signal around, so it's not pretty in code.
The reason to use a 3x clock (or higher) is that the BRAM should be guaranteed to have a full access time even if the clock synchronization is off a bit.