Reading more fine print in Programming the 65816 for my Crude Emulator, this time for the TXS instruction (because, yes, we're making progress with the stack system). And on page 416, I find this line: (My emphasis). So: The high byte of the Stack Pointer is set to $00, it claims, not $01. I found confirmation of this in the archives (viewtopic.php?f=5&t=255&p=2894&hilit=txs+65816#p2894), but am still a bit shocked, shocked I say, about what would seem to be rather counter-intuitive for anybody coming from the 6502. This is really the actual behavior?

Right, so if you're in native mode (816 mode) and for some reason you set index registers to 8 bits, then you have trouble doing TXS to initialise the stack. But if you did the init before you set to 8 bit mode, that should be OK. In which case you'd initialise X to $01FF before the TXS.

It's a five-mode chip, and that's one of the things that makes it hard to get your head around how best to make use of it.

Yes, you can set both X and M to 1 (ie select the 8-bit modes) but that's not the same as Emulation mode -- the latter has different wrap-around policy when an index potentially produces a page crossing. (There may be other differences, too -- I'm still learning this stuff!)

Something else to watch for is the asymmetry when moving between registers of different sizes. For example TAX and TXA:

Copying 8-bit X to 16-bit A means the destination high-byte gets filled with zeroes. But...
Copying 8-bit A to 16-bit X means the destination high-byte gets the (hidden) high-byte of the source! IOW,
Copying 8-bit A to 16-bit X is the same as
copying 16-bit A to 16-bit X.

If it helps (??), here's how I think about it. In the case of a mixed-size copy (X=1,M=0 or X=0,M=1) TXA and TAX are 16-bit operations. But X is incapable of containing ones in its high-byte when X =1 -- those bits are subject to a persistent and overriding reset. (Same for Y, of course.) X & Y aren't shortened when X =1 -- they remain 16-bit.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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The general rule in native mode is that the "size" of the data that is copied is dictated by the "width" of the destination register. If x=1 and m=0 in the status register then a copy from an index register to the accumulator is 16 bits, with bits 8-15 all cleared. Hence the accumulator will contain $00xx, where xx is the content of the index register.

There are some exceptions, in that the instructions TCD, TCS TDC and TSC always cause a 16 bit copy, no matter the setting of the m bit in SR.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yes, as you say,

if x=1 and m=0 then a copy from X/Y to A is 16 bits, with bits 8-15 all cleared. But I'm saying
if x=0 and m=1 then a copy from A to X/Y is 16 bits, with bits 8-15 preserved.

So I'm not quibbling -- merely drawing attention to some perhaps surprising behavior.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

EDIT: This is what happens when you get too much sleep for once in your life -- read the entry for TSC while thinking about TCS. The scary part is that it made sense at the time. Thanks to Dr. J!

Ignore this below, pls:

But wait, it gets even stanger! Now we're coding TCS, which you might assume would work the same way as TXS, just with the Accumulator. But no:

Quote:

If the A accumulator is set to just eight bits (whether because the m flag is set, or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the stack pointer and the hidden B accumulator takes the value of the high byte of the stack pointer.

So 8-bit native X moves "00xx" to S, when any sane person would expect "01xx", while 8-bit native A gives us "bbaa" and not "00aa", with "01aa" completely out of the question. Argh.

On days like this, I understand why people moved to the 68000 .

Maybe part of the trouble here is thinking that the stack naturally lives in page 1 - that's true in emulation mode, but not at all true in native mode. (In passing, the naming of these modes caused me brain strain at first, and to some extent still does - native to me sounds like normal, so that would be 6502 mode, whereas emulation sounds special, so that would be 816 mode. Except that's exactly wrong!)

It makes sense; because X can be 8 or 16 bits, whereas C means 16 bits, whether A includes B or not. It's not TAS, but TCS.

For the '816 in its native mode, page 1 has no special significance for the stack. It's no different from other pages.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?