I am trying to write a high level partial simulation of the 6551 front end (not the RS232 portion) so as to emulate a 6551 register set for a parallel port capability I am developing.

XMIT and RECV registers are easy, and the control reg is unneeded for my purposes. Only the lower 4 bits of the CMD register are needed (XMIT on and RECV IRQ enable), so those are easy as well.

I am, though, struggling with the status register reads. write is easy, as I do a soft reset of all the registers, but the datasheet does not seem to completely specify status bits behaviors. For instance:

bit 7 (IRQ): When the command register bit 1 is 0 (IRQs enabled), then I assume bit 7 of the status reg goes to 1 every time an IRQ fires. But, if bit 1 is 1 (IRQs disabled), does the IRQ bit go high when one of the conditions is met?

On receiver data register and transmit data register. I understand the flags goes to the other state when the reigsters are full/empty. But, if you read the status register, I assume these bits do not change, and if you don't handle the IRQ source, does the IRQ fire again (data arrives, rdr goes to 1, IRQ fires, user reads status reg, but then does *NOT* read data reg).

Or, is that the IRQ does not fire again until another byte arrives?

Does an IRQ fire when receive data is empty, or only when it is full? I assume only when it gets full...
Does an IRQ fire when transmit data register is full? I assume only when it is empty.

I've looked at the MOS and WDC datasheets, and neither helps me.

Jim

The data sheet should be fairly clear. In short, if you opt for no interrupts, you simply poll the status register to see if the data transmit register is empty or if the data receive register is full. Under interrupt mode, the chip will generate an IRQ every time the receive register is full and require the ISR handle it, thus clearing the the status register. Similarly, an IRQ will be generated when the transmit register can accept another character to send. If not serviced, it will go to a mark condition until your routine handles it and continuing generating interrupts. It's best to turn off the transmit interrupt when you don't need to send data. Receive interrupt can remain enabled as it will only generate an IRQ when data is received. Also note that if you don't handle the receive IRQ before another character is received a data overrun condition will be shown in the status register. Also note that the transmitter can generate an IRQ if CTS goes inactive, but there's no status register bit to show it, so if no status bits are active, CTS is a fallout.

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Regards, KM
https://github.com/floobydust

If the IC is orthagonal, and the transmit flag continues to IRQ until a data item is stored in the transmit register, I assume that if the Recv Full IRQ happens and you do not read the data, but you do read the status register, it will send another interrupt as soon as the status register is read.

I read both datasheets and did not see the CTS portion. Am I looking at the right one(s)?

Hmm, I wouldn't assume that. I'd assume the chip has an IRQ output which goes low (if interrupts are suitably enabled) when data arrives and is ready, or when data leaves and more can be sent, and goes high when the status register is read. That is, I'd assume an SR-flipflop type of behaviour.

Page 23 of the latest WDC datasheet (dated 24th October 2014) shows the recommended sequence for handling an IRQ generated by the 65C51. The last sentence (step 6) shows CTS as a fallout for the IRQ. I handle this in my BIOS as well and set a status byte in Page0 based on any error conditions in receive/transmit. I've also tested this extensively and CTS going high will create an interrupt. You can get the latest WDC datasheet from 65xx.com.

_________________
Regards, KM
https://github.com/floobydust

I've never used 6551, so my opinion is only surmise. But I expect the behavior is slightly more complex than that (or perhaps I misunderstand what you mean by SR-flipflop behaviour).

I expect there's a Full/Empty signal that originates from the Transmit register. A high-to-low transition on Full/Empty sets a flipflop, whose output is ANDed with Transmit_Interrupt_Enable. The AND output feeds a NOR whose output is the /IRQ pin.

Another Full/Empty signal originates from the Receive register. In this case it's a low-to-high transition that sets the associated flipflop. The FF output is ANDed with Receive_Interrupt_Enable, and that AND's output also feeds the NOR driving the /IRQ pin.

(Alternatively, there's no AND gate in each path, and instead each respective interrupt enable, when low, enforces an asynchronous Reset on the FF.)

Am I helping, or making matters worse?!

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks, I missed that portion on 23, but at least I know I was looking at the correct document.

JIm